态机的结构模式相对简单。状态机容易构成性能良好的同步时序逻
辑模块。状态机的VHDL表述丰富多样。在高速运算和控制方面，状态机更有其巨大的优势。就可靠性而言，状态机的优势也是十分明显的。2、时序进程将次态信号送到现态信号3、Moore型输出仅与当前状态有关，Mealy型输出是当前状态与所有输入信号
FSM:s_machinecurrent_stateclkPROCESSPROCESSREG
COMreset
ne_t_statestate_inputs
LIBRARYIEEE;
XXX.ALL;
ENTITYs_machineIS
PORT(clk,reset:INSTD_LOGIC;
state_inputs:INSTD_LOGIC_VECTOR(0TO1);
comb_outputs:OUTINTEGERRANGE0TO15);
ENDs_machine;
ARCHITECTUREbehvOFs_machineIS
TYPEFSM_STIS(s0,s1,s2,s3);
SIGNALcurrent_state,ne_t_state:FSM_ST;
BEGIN
REG:PROCESS(reset,clk)
BEGIN
IFreset='1'THENcurrent_state<=s0;
ELSIFclk='1'ANDclk'EVENTTHEN
current_state<=ne_t_state;
ENDIF;
ENDPROCESS;
COM:PROCESS(current_state,state_Inputs)
BEGIN
CASEcurrent_stateIS
WHENs0=>comb_outputs<=5;
IFstate_inputs="00"THENne_t_state<=s0;ELSEne_t_state<=s1;
ENDIF;
WHENs1=>comb_outputs<=8;
IFstate_inputs="00"THENne_t_state<=s1;
ELSEne_t_state<=s2;
ENDIF;
WHENs2=>comb_outputs<=12;
IFstate_inputs="11"THENne_t_state<=s0;
ELSEne_t_state<=s3;
ENDIF;
WHENs3=>comb_outputs<=14;
IFstate_inputs="11"THENne_t_state<=s3;
ELSEne_t_state<=s0;
ENDIF;
ENDcase;
ENDPROCESS;
ENDbehv;
三进程有限状态机
LIBRARYIEEE;
XXX.ALL;
ENTITYAD574IS
WHENOTHERS=>ne_t_state<=st0;ENDCASE;ENDPROCESSCOM1;COM2:PROCESS(current_state)BEGINCASEcurrent_stateISWHENst0=>CS<='1';A0<='1';RC<='1';LOCK<='0';WHENst1=>CS<='0';A0<='0';RC<='0';LOCK<='0';WHENst2=>CS<='0';A0<='0';RC<='0';LOCK<='0';WHENst3=>CS<='0';A0<='0';RC<='1';LOCK<='0';WHENst4=>CS<='0';A0<='0';RC<='1';LOCK<='1';WHENOTHERS=>CS<='1';A0<='1';RC<='1';LOCK<='0';ENDCASE;ENDPROCESSCOM2;REG:PROCESS(CLK)BEGINIF(CLK'EVENTANDCLK='1')THENcurrent_state<=ne_t_state;ENDIF;ENDPROCESSREG;LATCH1:PROCESS(LOCK)BEGINIFLOCK='1'ANDLOCK'EVENTTHENREGL<=D;ENDIF;ENDPROCESS;
Q<=REGL;ENDbehav;单进程Moore型有限状态机LIBRARYIEEE;XXX.ALL;ENTITYMOORE1ISPORT(DATAIN:INSTD_LOGIC_VECTOR(1DOWNTO0);CLK,RST:INSTD_LOGIC;Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDMOORE1;
ARCHITECTUREbehavOFMOORE1ISTYPEST_TYPEIS(ST0,ST1,ST2,ST3,ST4);SIGNALC_ST:ST_TYPE;BEGINPROCESS(CLK,RST)BEGINIFRST='1'THENC_ST<=ST0;Q<="0000";ELSIFCLK'EVENTANDCLK='1'THENCASEC_STIS
WHENST0=>IFDATAIN="10"THENC_ST<=ST1;ELSEC_ST<=ST0;ENDIF;Q<="1001";WHENST1=>IFDATAIN="11"THENC_ST<=ST2;ELSEC_ST<=ST1;ENDIF;Q<="0101";WHENST2=>IFDATAIN="01"THENC_ST<=ST3;ELSEC_ST<=ST0;ENDIF;Q<="1100";WHENST3=>IFDATAIN="00"THENC_ST<=ST4;ELSEC_ST<=ST2;ENDIF;Q<="0010";WHENST4=>IFDATAIN="11"THENC_ST<=ST0;ELSEC_ST<=ST3;ENDIF;Q<="1001";WHENOTHERS=>C_ST<=ST0;ENDCASE;ENDIF;ENDPROCESS;ENDbehav;2进程Mealy型有限状态机的设计LIBRARYIEEE;XXX.ALL;ENTITYMEALY1ISPORT(CLK,DATAIN,RESET:INSTD_LOGIC;Q:OUTSTD_LOGIC_VECTOR(4DOWNTO0));ENDMEALY1;ARCHITECTUREbehavOFMEALY1ISTYPEstatesIS(st0,st1,st2,st3,st4);SIGNALST_:states;BEGINCOMREG:PROCESS(CLK,RESET)BEGINIFRESET='1'THENST_<=ST0;ELSIFCLK'EVENTANDCLK='1'THENCASEST_ISWHENst0=>IFDATAIN='1'THENST_<=st1;ENDIF;WHENst1=>IFDATAIN='0'THENST_<=st2;ENDIF;WHENst2=>IFDATAIN='1'THENST_<=st3;ENDIF;WHENst3=>IFDATAIN='0'THENST_<=st4;ENDIF;WHENst4=>IFDATAIN='1'THENST_<=st0;ENDIF;WHENOTHERS=>ST_<=st0;ENDCASE;ENDIF;ENDPROCESSCOMREG;COM1:PROCESS(ST_,DATAIN)BEGINCASEST_IS
WHENst0=>IFDATAIN='1'THENQ<="10000";ELSEQ<="01010";ENDIF;WHENst1=>IFDATAIN='0'THENQ<="10111";ELSEQ<="10100";ENDIF;WHENst2=>IFDATAIN='1'THENQ<="10101";ELSEQ<="10011";ENDIF;WHENst3=>IFDATAIN='0'THENQ<="11011";ELSEQ<="01001";ENDIF;WHENst4=>IFDATAIN='1'THENQ<="11101";ELSEQ<="01101";ENDIF;WHENOTHERS=>Q<="00000";ENDCASE;ENDPROCESSCOM1;ENDbehav;状态编码LIBRARYIEEE;XXX.ALL;ENTITYAD574AISPORT(D:INSTD_LOGIC_VECTOR(11DOWNTO0);CLK,STATUS:INSTD_LOGIC;OUT4:OUTSTD_LOGIC_VECTOR(3ENDCASE;OUT4<=current_state(4DOWNTO1);ENDPROCESSCOM1;
REG:PROCESS(CLK)BEGINIF(CLK'EVENTANDCLK='1')THENcurrent_state<=ne_t_state;ENDIF;
ENDPROCESSREG;
LK<=current_state(1);LATCH1:PROCESS(LK)
BEGIN
IFLK='1'ANDLK'EVENTTHEN
REGL<=D;ENDIF;ENDPROCESS;Q<=REGL;
ENDbehav;
9章1、VHDL有那几种基本的顺序语句赋值语句;流程控制语句;等待语句;子程序调用语句;返回语句;空操作语句。2、什么叫顺序语句，它的适用范围是什么
执行顺序与它们的书写顺序基本一致的语句叫顺序语句，顺序语句只能出现在进程和子程序中，子程序包括函数和过程。3、VHDL并行语句几种并行信号赋值语句;进程语句;块语句;条件信号赋值语句;元件例化语句;生成语句;并行过程调用语句。4、什么叫并行语句在结构体的执行是同步进行的，或者说是并行运行的，其执行方式与书写的顺序无关。
5、VHDL中具有属性的项目：类型、子类型、过程、函数、信号、变量、常量、实体、结构体、配置、程序包、元件和语句标号等。6、综合器支持的属性有：LEFT、RIGHT、HIGH、LOW、RANGE、REVERSRANGE、LENGTH、EVENT及STABLE。
端口模式：IN单向只读OUT单向输出INOUT输入输出双向BUFFER内部回读输出信号，反馈数据类型：INTEGER整数数据BOOLEAN布尔数据STD_LOGIC标准逻辑位数据BIT位数据逻辑操作符：AND与OR或NAND与非NOR或非_OR异或_NOR同或NOT非数据对象：SIGNAL信号VARIABLE变量CONSTANT常量7、for_loop语句实现一个16位的串行并出移位寄存器
LibraryIEEE;XXX.all;XXX.all;XXX.all;Entitychuan_bingisport(load:instd_logic;
d_in:instd_logic;d_out:bufferstd_logic_vector(15downto0);clk:instd_logic);
endchuan_bing;architecturearchofchuan_bingissignall:std_logic_vector(15downto0);beginprocess(clk)beginif(clk'eventandclk='1')thenl(0)<=d_in;if(load='0')thenforiin14downto0loopl(i+1)<=l(i);endloop;elsed_out<=l;endif;endif;endprocess;endarch;
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