from Texas
Instruments
FEATURES APPLICATIONS
DESCRIPTION
BYTE
16-/8-Bit
Parallel DATA
Output Bus
CONVST
BUSY
CS
RD
RESET REFOUT
ADS8411
SLAS369B–APRIL2002–REVISED DECEMBER2004 16-BIT,2MSPS,UNIPOLAR INPUT,MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE
•DWDM
•2-MHz Sample Rate
•Instrumentation
•16-Bit NMC Ensured Over Temperature
•High-Speed,High-Resolution,Zero Latency •Zero Latency
Data Acquisition Systems
•Unipolar Single-Ended Input Range:
•Transducer Interface
0V to V ref
•Medical Instruments
•Onboard Reference
•Communication
•Onboard Reference Buffer
•High-Speed Parallel Interface
•Power Dissipation:175mW at2MHz Typ The ADS8411is a16-bit,2MHz A/D converter with •Wide Digital Supply an internal4.096-V reference.The device includes a
16-bit capacitor-based SAR A/D converter with in-•8-/16-Bit Bus Transfer
herent sample and hold.The ADS8411offers a full •48-Pin TQFP Package
16-bit interface and an8-bit option where data is read •ESD Sensitive–HBM Capability of500V,using two8-bit read cycles.
1000V at All Input Pins
The ADS8411has a unipolar single-ended input.It is
available in a48-lead TQFP package and is
characterized over the industrial-40°C to85°C tem-
perature range.
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.Copyright©2002–2004,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas
Instruments standard warranty.Production processing does not
necessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
ADS8411
SLAS369B–APRIL 2002–REVISED DECEMBER 2004
This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
MAXIMUM MAXIMUM NO MISSING PACKAGE TEMPERA-TRANSPORT INTEGRAL DIFFERENTIAL CODES PACKAGE ORDERING MODEL
DESIG-TURE MEDIA LINEARITY LINEARITY RESOLUTION
TYPE
INFORMATION NATOR
RANGE
QUANTITY (LSB)
(LSB)
(BIT)
Tape and reel
ADS8411IPFBT
25048Pin ADS8411I –6~6–2~315
PFB
–40°C to 85°C
TQFP
Tape and reel
ADS8411IPFBR 1000Tape and reel
ADS8411IBPFBT
25048Pin ADS8411IB –2.5~2.5–1~216
PFB
–40°C to 85°C
TQFP
Tape and reel
ADS8411IBPFBR
1000
(1)For the most current specifications and package information,refer to our website at www.ti.com.
over operating free-air temperature range unless otherwise noted (1)
UNIT
+IN to AGND –0.4V to +VA +0.1V
Voltage
–IN to AGND –0.4V to 0.5V +VA to AGND
–0.3V to 7V Voltage range
+VBD to BDGND –0.3V to 7V +VA to +VBD
–0.3V to 2.55V Digital input voltage to BDGND –0.3V to +VBD +0.3V Digital output voltage to BDGND
–0.3V to +VBD +0.3V
T A Operating free-air temperature range –40°C to 85°C T stg
Storage temperature range –65°C to 150°C
Junction temperature (T J max)150°C Power dissipation (T J Max -T A )/θJA
TQFP package
θJA thermal impedance
86°C/W Vapor phase (60sec)215°C Lead temperature,soldering
Infrared (15sec)
220°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
ADS8411 SLAS369B–APRIL2002–REVISED DECEMBER2004
T A =–40°C to85°C,+VA=5V,+VBD=3V or5V,V
ref
=4.096V,f
SAMPLE
=2MHz(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input voltage(1)+IN–(–IN)0V ref V
+IN–0.2V ref+0.2 Absolute input voltage V
–IN–0.20.2 Input capacitance25pF
Input leakage current0.5nA SYSTEM PERFORMANCE
Resolution16Bits
ADS8411I15
No missing codes Bits
ADS8411IB16
ADS8411I–6±46
INL Integral linearity(2)(3)LSB
ADS8411IB–2.5±1.5 2.5
ADS8411I–2±13
DNL Differential linearity LSB
ADS8411IB–1±0.82
ADS8411I–1.5±0.5 1.5mV
E O Offset error(4)
ADS8411IB–0.75±0.250.75mV
ADS8411I–0.150.15
E G Gain error(4)(5)%FS
ADS8411IB–0.0980.098 Noise60µV RMS
At FFFFh output code,
PSRR DC Power supply rejection ratio+VA=4.75V to5.25V,2LSB
V ref=4.096V(4)
SAMPLING DYNAMICS
Conversion time340400ns
Acquisition time100ns
Throughput rate2MHz Aperture delay2ns
Aperture jitter25ps
Step response100ns
Overvoltage recovery100ns DYNAMIC CHARACTERISTICS
V IN=4V pp at100kHz–90dB THD Total harmonic distortion(6)
V IN=4V pp at500kHz–88.5dB SNR Signal-to-noise ratio V IN=4V pp at100kHz86dB SINAD Signal-to-noise+distortion V IN=4V pp at100kHz85dB
V IN=4V pp at100kHz90dB SFDR Spurious free dynamic range
V IN=4V pp at500kHz88dB -3dB Small signal bandwidth5MHz EXTERNAL VOLTAGE REFERENCE INPUT
Reference voltage at REFIN,V ref 3.9 4.096 4.2V
Reference resistance(7)500kΩ
(1)Ideal input span,does not include gain or offset error.
(2)LSB means least significant bit
(3)This is endpoint INL,not best fit.
(4)Measured relative to an ideal full-scale input[+IN–(–IN)]of4.096V
(5)This specification does not include the internal reference voltage error and drift.
(6)Calculated on the first nine harmonics of the input frequency
(7)Can vary±20%
3
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ADS8411
SLAS369B–APRIL 2002–REVISED DECEMBER 2004
SPECIFICATIONS (continued)
T A =–40°C to 85°C,+VA =5V,+VBD =3V or 5V,V ref =4.096V,f SAMPLE =2MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL REFERENCE OUTPUT
From 95%(+VA),with 1Internal reference start-up time
120ms µF storage capacitor V ref
Reference voltage IOUT =0 4.065
4.096
4.13V Source current Static load
10
µA Line regulation +VA =4.75~5.25V 0.6mV Drift
IOUT =0
36
PPM/°C
DIGITAL INPUT/OUTPUT
Logic family —CMOS
V IH High level input voltage I IH =5µA +VBD –1
+VBD +0.3
V IL Low level input voltage I IL =5µA –0.3
0.8V
V OH High level output voltage I OH =2TTL loads +VBD –0.6
+VBD V OL
Low level output voltage I OL =2TTL loads
0.4
Data format —straight binary
POWER SUPPLY REQUIREMENTS
+VBD 2.73 5.25V Power supply voltage +VA
4.75
5 5.25V +VA Supply current (8)
f s =2MHz 3538mA P D Power dissipation (8)f s =2MHz
175
190
mW
TEMPERATURE RANGE
T A Operating free-air
–40
85
°C
(8)
This includes only +VA current.+VBD current is typically 1mA with 5-pF load capacitance on output pins.
4
TIMING CHARACTERISTICS
ADS8411 SLAS369B–APRIL2002–REVISED DECEMBER2004
All specifications typical at–40°C to85°C,+VA=+VBD=5V(1)(2)(3)
PARAMETER MIN TYP MAX UNIT
t CONV Conversion time340400ns
t ACQ Acquisition time100ns
t pd1CONVST low to BUSY high30ns
t pd2Propagation delay time,end of conversion to BUSY low5ns
t w1Pulse duration,CONVST low20ns
t su1Setup time,CS low to CONVST low0ns
t w2Pulse duration,CONVST high20ns
CONVST falling edge jitter10ps
t w3Pulse duration,BUSY signal low Min(t ACQ)ns
t w4Pulse duration,BUSY signal high370ns
Hold time,first data bus data transition(RD low,or CS low for read
t h140ns cycle,or BYTE input changes)after CONVST low
t d1Delay time,CS low to RD low(or BUSY low to RD low)0ns
t su2Setup time,RD high to CS high0ns
t w5Pulse duration,RD low50ns
t en Enable time,RD low(or CS low for read cycle)to data valid20ns
t d2Delay time,data hold from RD high0ns
t d3Delay time,BYTE rising edge or falling edge to data valid220ns
t w6Pulse duration,RD high20ns
t w7Pulse duration,CS high20ns
Hold time,last RD(or CS for read cycle)rising edge to CONVST
t h250ns falling edge
t su3Setup time,BYTE transition to RD falling edge0ns
t h3Hold time,BYTE transition to RD falling edge0ns
t dis Disable time,RD high(CS high for read cycle)to3-stated data bus20ns
t d5Delay time,end of conversion to MSB data valid10ns
Byte transition setup time,from BYTE transition to next BYTE
t su450ns transition
t d6Delay time,CS rising edge to BUSY falling edge50ns
t d7Delay time,BUSY falling edge to CS rising edge50ns
Setup time,from the falling edge of CONVST(used to start the valid
conversion)to the next falling edge of CONVST(when CS=0and
t su(AB)60340ns CONVST used to abort)or to the next falling edge of CS(when CS is
used to abort)
Setup time,falling edge of CONVST to read valid data(MSB)from
t su5MAX(t CONV)+MAX(t d5)ns current conversion
Hold time,data(MSB)from previous conversion hold valid from
t h4MIN(t CONV)ns falling edge of CONVST
(1)All input signals are specified with t r=t f=5ns(10%to90%of+VBD)and timed from a voltage level of(V IL+V IH)/2.
(2)See timing diagrams.
(3)All timings are measured with20pF equivalent loads on all data bits and BUSY pins.
5
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TIMING CHARACTERISTICS
ADS8411
SLAS369B–APRIL 2002–REVISED DECEMBER 2004
All specifications typical at –40°C to 85°C,+VA =5V,+VBD =3V (1)(2)(3)
PARAMETER
MIN TYP
MAX UNIT t CONV Conversion time 340400
ns t ACQ Acquisition time
100
ns t pd1CONVST low to conversion started (BUSY high)40ns t pd2Propagation delay time,end of conversion to BUSY low 10ns t w1Pulse duration,CONVST low 20ns t su1Setup time,CS low to CONVST low 0ns t w2Pulse duration,CONVST high 20
ns CONVST falling edge jitter 10
ps t w3Pulse duration,BUSY signal low Min(t ACQ )
ns t w4Pulse duration,BUSY signal high
370
ns Hold time,first data bus transition (RD low,or CS low for read cycle,t h140ns or BYTE input changes)after CONVST low
t d1Delay time,CS low to RD low (or BUSY low to RD low)0ns t su2Setup time,RD high to CS high 0ns t w5Pulse duration,RD low
50
ns t en Enable time,RD low (or CS low for read cycle)to data valid 30
ns t d2Delay time,data hold from RD high
0ns t d3Delay time,BYTE rising edge or falling edge to data valid 230
ns t w6Pulse duration,RD high 20ns t w7Pulse duration,CS high
20ns Hold time,last RD (or CS for read cycle )rising edge to CONVST t h250ns falling edge
t su3Setup time,BYTE transition to RD falling edge 0ns t h3Hold time,BYTE transition to RD falling edge
ns t dis Disable time,RD high (CS high for read cycle)to 3-stated data bus 30ns t d5Delay time,end of conversion to MSB data valid
20ns Byte transition setup time,from BYTE transition to next BYTE t su450ns transition
t d6Delay time,CS rising edge to BUSY falling edge 50ns t d7Delay time,BUSY falling edge to CS rising edge
50ns Setup time,from the falling edge of CONVST (used to start the valid conversion)to the next falling edge of CONVST (when CS =0and t su(AB)
70
350
ns
CONVST used to abort)or to the next falling edge of CS (when CS is used to abort)
Setup time,falling edge of CONVST to read valid data (MSB)from t su5MAX(t CONV )+MAX(t d5)
ns current conversion
Hold time,data (MSB)from previous conversion hold valid from t h4MIN(t CONV )
ns
falling edge of CONVST
(1)All input signals are specified with t r =t f =5ns (10%to 90%of +VBD)and timed from a voltage level of (V IL +V IH )/2.(2)See timing diagrams.
(3)
All timings are measured with 20pF equivalent loads on all data bits and BUSY pins.
6
PIN ASSIGNMENTS
NC - No connection
+VBD DB8DB9DB10DB11DB12DB13DB14DB15AGND AGND +VA
PFB PACKAGE (TOP VIEW)
D B 4D B 5D B 6D B 7B U S Y B D G N D +V B D D B 0D B 1D B 2D B 3A G N +V +V R
E
F I R E F O U N +V A
G N +I -I N A G N A G N B D G N DTerminal Functions
NAME NO.I/O DESCRIPTION
AGND5,8,11,12,14,–Analog ground
15,44,45
BDGND25,35–Digital ground for bus interface digital supply
BUSY36O Status output.High when a conversion is in progress.
BYTE39I Byte select input.Used for8-bit bus reading.0:No fold back1:Low byte D[7:0]of the16most
significant bits is folded back to high byte of the16most significant pins DB[15:8].
CONVST40I Convert start.The falling edge of this input ends the acquisition period and starts the hold
period.
CS42I Chip select.The falling edge of this input starts the acquisition period.
8-Bit Bus16-Bit Bus
Data Bus
BYTE=0BYTE=1BYTE=0
DB1516O D15(MSB)D7D15(MSB)
DB1417O D14D6D14
DB1318O D13D5D13
DB1219O D12D4D12
DB1120O D11D3D11
DB1021O D10D2D10
DB922O D9D1D9
DB823O D8D0(LSB)D8
DB726O D7All ones D7
DB627O D6All ones D6
DB528O D5All ones D5
DB429O D4All ones D4
DB330O D3All ones D3
DB231O D2All ones D2
DB132O D1All ones D1
DB033O D0(LSB)All ones D0(LSB)
–IN7I Inverting input channel
+IN6I Non inverting input channel
NC3–No connection
REFIN1I Reference input
REFM47,48I Reference ground
REFOUT2O Reference output.Add1µF capacitor between the REFOUT pin and REFM pin when internal
reference is used.
RESET38I Current conversion is aborted and output latches are cleared(set to zeros)when this pin is
asserted low.RESET works independantly of CS.
RD41I Synchronization pulse for the parallel output.When CS is low,this serves as the output enable
and puts the previous conversion result on the bus.
+VA4,9,10,13,43,–Analog power supplies,5-V dc
46
+VBD24,34,37–Digital power supply for busTIMING DIAGRAMS
†Signal internal to device
Figure1.Timing for Conversion and Acquisition Cycles With CS and RD Toggling
Figure2.Timing for Conversion and Acquisition Cycles With CS Toggling,RD Tied to BDGND
†Signal internal to device
Figure3.Timing for Conversion and Acquisition Cycles With CS Tied to BDGND,RD Toggling
†Signal internal to device
Figure4.Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND—Auto Read
RD
BYTE
DB[15:0]
Figure5.Detailed Timing for Read Cycles
TYPICAL CHARACTERISTICS
−40
−20
020406080
S N R − S i g n a l -t o -N o i s e R a t i o − d B
T A − Free-Air Temperature − °C
10000
20000300004000050000600007000065230
65239
65235
13.25
13.313.3513.4
13.4513.513.5513.6
E N O B − E f f e c t i v e N u m b e r o f B i t s − B i t s
T A − Free-Air Temperature − °C
81.6
81.88282.282.482.682.88383.283.483.683.8
−40
−20
020406080
S I N A D − S i g n a l -t o -N o i s a n d D i s t o r t i o n − d B
T A − Free-Air Temperature − °C
At –40°C to 85°C,+VA =5V,+VBD =5V,REFIN =4.096V (internal reference used)and f sample =2MHz (unless otherwise noted)
HISTOGRAM (DC CODE SPREAD)
SIGNAL-TO-NOISE RATIO
vs
vs
FULL SCALE 131071CONVERSIONS
FREE-AIR TEMPERATURE
Figure 6.
Figure 7.
SIGNAL-TO-NOISE AND DISTORTION
EFFECTIVE NUMBER OF BITS
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 8.Figure 9.
T A − Free-Air Temperature − °C
S F D R − S p u r i o u s F r e e D y n a m i c R a n g e − d B
−94.5
−94−93.5−93−92.5−92−91.5−91
T A − Free-Air Temperature − °C
T H D − T o t a l H a r m o n i c D i s t o r t i o n − d B
20
406080
100
S N R − S i g n a l -t o -N o i s e R a t i o − d B
f i − Input Frequency − kHz
20
406080
100
E N O B − E f f e c t i v e N u m b e r o f B i t s − B i t s
f i − Input Frequency − kHz
SPURIOUS FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 10.
Figure 11.
SIGNAL-TO-NOISE RATIO
EFFECTIVE NUMBER OF BITS
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
Figure 12.Figure 13.
20
406080
100
f i − Input Frequency − kHz
S F D R − S p u r i o u s F r e e D y n a m i c R a n g e − d B
8384
85
S I N A D − S i g n a l -t o -N o i s a n d D i s t o r t i o n − d B
f i − Input Frequency − kHz
−101
−100−99−98−97−96−95−94−93−920
20
406080
100
f i − Input Frequency − kHz
T H D − T o t a l H a r m o n i c D i s t o r t i o n − d B
28.5
2929.53030.53131.53232.53333.5500
700
900
11001300150017001900
I C C − S u p p l y C u r r e n t − m A
Samply Rate − KSPS
SIGNAL-TO-NOISE AND DISTORTION
SPURIOUS FREE DYNAMIC RANGE
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
Figure 14.
Figure 15.TOTAL HARMONIC DISTORTION
SUPPLY CURRENT
vs
vs
INPUT FREQUENCY
SAMPLE RATE
Figure 16.Figure 17.
00.05
0.10
0.15
0.200.25
4.75
4.85 4.95
5.05 5.15
5.25
V DD − Supply Voltage − V
− G a i n E r r o r − m V
E
G
4.75
4.85 4.95
5.05
5.15 5.25
− O f f s e t E r r o r − m V
E O V DD − Supply Voltage − V
−40
−20
020406080
I n t e r n a l V o l t a g e R e f e r e n c e − V
T A − Free-Air Temperature − °
C
−40
−20
20406080
− G a i n E r r o r − m V
E G T A − Free-Air Temperature − °C
GAIN ERROR
OFFSET ERROR
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
Figure 18.
Figure 19.
INTERNAL VOLTAGE REFERENCE
GAIN ERROR
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 20.Figure 21.
−40
−200204060
80
− O f f s e t E r r o r − m V
E O T A − Free-Air Temperature − °
C
−40
−200204060
80
T A − Free-Air Temperature − °C
I C C − S u p p l y C u r r e n t − m
A
−1.5−1−0.5
00.511.52
−40
−20
020406080
T A − Free-Air Temperature − °C
D N L − D i f f e r e n t i a l N o n l i n e a r i t y − L S B s
T A − Free-Air Temperature − °C
I N L − I n t e g r a l N o n l i n e a r i t y − L S B s
OFFSET ERROR
SUPPLY CURRENT
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 22.
Figure 23.
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
Figure 24.Figure 25.
012340
3276865536
D N L − L S B s
Code 16384
49152
16384
65536
I N L − L S B s
Code 3276849152
−160−180
100
200
300
400
500
600
−100−600700
800
900
−140−120−80−40−20
M a g n i t u d e − d B
Frequency − kHz
1000
DNL
Figure 26.
INL
Figure 27.
FFT
Figure 28.
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APPLICATION INFORMATION
MICROCONTROLLER INTERFACING
ADS8411to 8-Bit Microcontroller Interface
Analog 5 V
Ext Ref Input
Analog Input
Analog 5 V
AGND
PRINCIPLES OF OPERATION
ADS8411
SLAS369B–APRIL 2002–REVISED DECEMBER 2004
Figure 29shows a parallel interface between the ADS8411and a typical microcontroller using the 8-bit data bus.The BUSY signal is used as a falling-edge interrupt to the microcontroller.
Figure 29.ADS8411Application Circuitry (using external reference)
Figure 30.Use Internal Reference
The ADS8411is a high-speed successive approximation register (SAR)analog-to-digital converter (ADC).The architecture is based on charge redistribution,which inherently includes a sample/hold function.See Figure 29for the application circuit for the ADS8411.
The conversion clock is generated internally.The conversion time of 400ns is capable of sustaining a 2-MHz throughput.
19
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REFERENCE
ANALOG INPUT
DIGITAL INTERFACE
Timing And Control
ADS8411
SLAS369B–APRIL 2002–REVISED DECEMBER 2004
PRINCIPLES OF OPERATION (continued)
The analog input is provided to two input pins:+IN and –IN.When a conversion is initiated,the differential input on these pins is sampled on the internal capacitor array.While a conversion is in progress,both inputs are disconnected from any internal function.
The ADS8411can operate with an external reference with a range from 3.9V to 4.2V.A 4.096-V internal reference is included.When the internal reference is used,pin 2(REFOUT)should be connected to pin 1(REFIN)with 0.1-µF decoupling capacitor and 1-µF storage capacitor between pin 2(REFOUT)and pins 47and 48(REFM)(see Figure 30).The internal reference of the converter is double buffered.If an external reference is used,the second buffer provides isolation between the external reference and the CDAC.This buffer is also used to recharge all of the capacitors of the CDAC during conversion.Pin 2(REFOUT)can be left unconnected (floating)if an external reference is used.
When the converter enters the hold mode,the voltage difference between the +IN and -IN inputs is captured on the internal capacitor array.The voltage on the –IN input is limited between –0.2V and 0.2V,allowing the input to reject small signals which are common to both the +IN and –IN inputs.The +IN input has a range of –0.2V to V ref +0.2V.The input span (+IN –(–IN))is limited to 0V to V ref .
The input current on the analog inputs depends upon a number of factors:sample rate,input voltage,and source impedance.Essentially,the current into the ADS8411charges the internal capacitor array during the sample period.After this capacitance has been fully charged,there is no further input current.The source of the analog input voltage must be able to charge the input capacitance (25pF)to an 16-bit settling level within the acquisition time (100ns)of the device.When the converter goes into the hold mode,the input impedance is greater than 1G Ω.
Care must be taken regarding the absolute analog input voltage.To maintain the linearity of the converter,the +IN and –IN inputs and the span (+IN –(–IN))should be within the limits specified.Outside of these ranges,the converter's linearity may not meet specifications.To minimize noise,low bandwidth input signals with low-pass filters should be used.
Care should be taken to ensure that the output impedance of the sources driving +IN and –IN inputs are matched.If this is not observed,the two inputs could have different setting time.This may result in offset error,gain error and linearity error which varies with temperature and input voltage.
See the timing diagrams in the specifications section for detailed information on timing signals and their requirements.
The ADS8411uses an internal oscillator generated clock which controls the conversion rate and in turn the throughput of the converter.No external clock input is required.
Conversions are initiated by bringing the CONVST pin low for a minimum of 20ns (after the 20ns minimum requirement has been met,the CONVST pin can be brought high),while CS is low.The ADS8411switches from the sample to the hold mode on the falling edge of the CONVST command.A clean and low jitter falling edge of this signal is important to the performance of the converter.The BUSY output is brought high after CONVST goes low.BUSY stays high throughout the conversion process and returns low when the conversion has ended.Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS when BUSY is low.
Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST goes low to initiate a conversion).Both the RD and CS pins are brought low in order to enable the parallel output bus with the conversion.
20
RESET
ADS8411 SLAS369B–APRIL2002–REVISED DECEMBER2004
PRINCIPLES OF OPERATION(continued)
The ADS8411outputs full parallel data in straight binary format as shown in Table1.The parallel output is active when CS and RD are both low.There is a minimal quiet zone requirement around the falling edge of CONVST. This is50ns prior to the falling edge of CONVST and40ns after the falling edge.No data read should be attempted within this zone.Any other combination of CS and RD sets the parallel output to3-state.BYTE is used for multiword read operations.BYTE is used whenever lower bits of the converter result are output on the higher byte of the bus.Refer to Table1for ideal output codes.
Table1.Ideal Input Voltages and Output Codes
DESCRIPTION ANALOG VALUE DIGITAL OUTPUT
Full scale range V ref STRAIGHT BINARY
Least significant bit(LSB)V ref/65536BINARY CODE HEX CODE
Full scale V ref–1LSB1111111111111111FFFF
Midscale V ref/210000000000000008000
Midscale–1LSB V ref/2–1LSB01111111111111117FFF
Zero0V00000000000000000000
The output data is a full16-bit word(D15–D0)on DB15–DB0pins(MSB-LSB)if BYTE is low.
The result may also be read on an8-bit bus for convenience.This is done by using only pins DB15-DB8.In this case two reads are necessary:the first as before,leaving BYTE low and reading the8most significant bits on pins DB15-DB8,then bringing BYTE high.When BYTE is high,the low bits(D7–D0)appear on pins DB15–D8. These multiword read operations can be done with multiple active RD(toggling)or with RD tied low for simplicity.
Table2.Conversion Data Readout
DATA READ OUT
BYTE
DB15–DB8Pins DB7-DB0Pins
High D7–D0All one's
Low D15–D8D7-D0
RESET is an asynchronous active low input signal(that works independently of CS).Minimum RESET low time is25ns.Current conversion will be aborted no later than50ns after the converter is in the reset mode.In addition,all output latches are cleared(set to zero's)after RESET.The converter goes back to normal operation mode no later than20ns after RESET input is brought high.
The converter starts the first sampling period20ns after the rising edge of RESET.Any sampling period except for the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling edge of CS,whichever is later.
Another way to reset the device is through the use of the combination of CS and CONVST.This is useful when the dedicated RESET pin is tied to the system reset but there is a need to abort only the conversion in a specific converter.Since the BUSY signal is held high during the conversion,either one of these conditions triggers an internal self-clear reset to the converter just the same as a reset via the dedicated RESET pin.The reset does not have to be cleared as for the dedicated RESET pin.A reset can be started with either of the two following steps.
•Issue a CONVST when CS is low and a conversion is in progress.The falling edge of CONVST must satisfy the timing as specified by the timing parameter t su(AB)mentioned in the timing characteristics table to ensure
a reset.The falling edge of CONVST starts a reset.Timing is the same as a reset using the dedicated
RESET pin except the instance of the falling edge is replaced by the falling edge of CONVST.
•Issue a CS while a conversion is in progress.The falling edge of CS must satisfy the timing as specified by the timing parameter t su(AB)mentioned in the timing characteristics table to ensure a reset.The falling edge of CS causes a reset.Timing is the same as a reset using the dedicated RESET pin except the instance of the falling edge is replaced by the falling edge of CS.
21
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POWER-ON INITIALIZATION
LAYOUT
ADS8411
SLAS369B–APRIL 2002–REVISED DECEMBER 2004
RESET is not required after power on.An internal power-on-reset circuit generates the reset.To ensure that all of the registers are cleared,the three conversion cycles must be given to the converter after power on.
For optimum performance,care should be taken with the physical layout of the ADS8411circuitry.
As the ADS8411offers single-supply operation,it is often used in close proximity with digital logic,microcontrollers,microprocessors,and digital signal processors.The more digital logic present in the design and the higher the switching speed,the more difficult it is to achieve good performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply,reference,ground connections and digital inputs that occur just prior to latching the output of the analog comparator.Thus,driving any single conversion for an n-bit SAR converter,there are at least n windows in which large external transient voltages can affect the conversion result.Such glitches might originate from switching power supplies,nearby digital logic,or high power devices.
The degree of error in the digital output depends on the reference voltage,layout,and the exact timing of the external event.
On average,the ADS8411draws very little current from an external reference,as the reference voltage is internally buffered.If the reference voltage is external and originates from an op amp,make sure that it can drive the bypass capacitor or capacitors without oscillation.A 0.1-µF bypass capacitor and a 1-µF storage capacitor are recommended from pin 1(REFIN)directly to pin 48(REFM).REFM and AGND should be shorted on the same ground plane under the device.
The AGND and BDGND pins should be connected to a clean ground point.In all cases,this should be the analog ground.Avoid connections which are close to the grounding point of a microcontroller or digital signal processor.If required,run a ground trace directly from the converter to the power supply entry point.The ideal layout consists of an analog ground plane dedicated to the converter and associated analog circuitry.
As with the AGND connections,+VA should be connected to a 5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point.Power to the ADS8411should be clean and well bypassed.A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible.See Table 3for the placement of the capacitor.In addition,a 1-µF to 10-µF capacitor is recommended.In some situations,additional bypassing may be required,such as a 100-µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the 5-V supply,removing the high frequency noise.
Table 3.Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
CONVERTER ANALOG SIDE CONVERTER DIGITAL SIDE SUPPLY PINS
(4,5),(8,9),(10,11),(13,15),Pin pairs that require shortest path to decoupling capacitors (24,25),(34,35)(43,44),(45,46)Pins that require no decoupling
12,14
37
22
Orderable Device Status (1)Package Type Package
Drawing Pins Package Qty Eco Plan (2)Lead/
Ball Finish
MSL Peak Temp (3)Samples
(Requires Login)
ADS8411IBPFBR ACTIVE TQFP PFB481000Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
ADS8411IBPFBRG4ACTIVE TQFP PFB481000Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Purchase Samples
ADS8411IBPFBT ACTIVE TQFP PFB48250Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
ADS8411IBPFBTG4ACTIVE TQFP PFB48250Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
ADS8411IPFBT ACTIVE TQFP PFB48250Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
ADS8411IPFBTG4ACTIVE TQFP PFB48250Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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TAPE AND REEL INFORMATION
*All dimensions are nominal Device Package Type Package Drawing
Pins
SPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant ADS8411IBPFBR TQFP
PFB 481000330.016.49.69.6 1.512.016.0Q2ADS8411IBPFBT TQFP
PFB 48250330.016.49.69.6 1.512.016.0Q2ADS8411IPFBT TQFP PFB 48250
330.016.49.69.6 1.512.016.0Q2
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) ADS8411IBPFBR TQFP PFB481000346.0346.033.0 ADS8411IBPFBT TQFP PFB48250346.0346.033.0
ADS8411IPFBT TQFP PFB48250346.0346.033.0
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