视频1 视频21 视频41 视频61 视频文章1 视频文章21 视频文章41 视频文章61 推荐1 推荐3 推荐5 推荐7 推荐9 推荐11 推荐13 推荐15 推荐17 推荐19 推荐21 推荐23 推荐25 推荐27 推荐29 推荐31 推荐33 推荐35 推荐37 推荐39 推荐41 推荐43 推荐45 推荐47 推荐49 关键词1 关键词101 关键词201 关键词301 关键词401 关键词501 关键词601 关键词701 关键词801 关键词901 关键词1001 关键词1101 关键词1201 关键词1301 关键词1401 关键词1501 关键词1601 关键词1701 关键词1801 关键词1901 视频扩展1 视频扩展6 视频扩展11 视频扩展16 文章1 文章201 文章401 文章601 文章801 文章1001 资讯1 资讯501 资讯1001 资讯1501 标签1 标签501 标签1001 关键词1 关键词501 关键词1001 关键词1501 专题2001
Verilog HDL洗衣机控制器
2025-10-01 21:02:17 责编:小OO
文档
定义5种状态,零停机、一设定时间、二漂洗、三洗涤、四脱水,要求设定时间给漂洗,漂洗正反转各10秒,洗涤正反转各5秒,脱水正反转各1秒,有一个设定时间键,有一个切换模式键,四种工作状态分别有四个LED显示。

mod 切换模式,一共有停机s0,调整时间s1,漂洗s2,洗涤s3,脱水s4,共五种状态

add 为调整时间累加,最后赋给timecount

piaocount 是漂洗计数

xicount是洗涤计数

tuocount是脱水计数

zheng表示电机正转

fan表示电机反转

module wash(mod,add,led1,led2,led3,led4,clk,zheng,fan);

input mod,add,clk;

output led1,led2,led3,led4,zheng,fan;

reg led1,led2,led3,led4;

reg zheng,fan;

reg [9:0] timecount,counter;

reg [4:0] piaocount,xicount,tuocount;

reg [2:0] state;

parameter s0=3'b000;

parameter s1=3'b001;

parameter s2=3'b010;

parameter s3=3'b011;

parameter s4=3'b100;

always @(posedge add)

      begin

if(counter<600)

counter<=counter+10'd60;

        else

counter<=0;

      end 

   

always @(posedge clk)

begin

   begin 

zheng<=0;

fan<=0;

   end 

   case(state)

     s0:

        begin

zheng<=0;fan<=0;

timecount<=0;

led1<=1'b0;

led2<=1'b0;

led3<=1'b0;

led4<=1'b0;

piaocount<=5'b00000;

xicount<=5'b00000;

tuocount<=5'b00000;

          if(mod)

state<=s1;

          else 

state<=s0;

        end

   

     s1:begin

led1<=1'b1;

led2<=1'b0;

led3<=1'b0;

led4<=1'b0;

           begin

timecount<=counter;

           end

           if(mod)

state<=s2;

           else 

state<=s1;

        end

     

      s2:begin

led1<=1'b0;

led2<=1'b1;

led3<=1'b0;

led4<=1'b0;

piaocount<=5'b00000;

xicount<=5'b00000;

tuocount<=5'b00000;

               if(mod)

state<=s3;

               else 

state<=s2;

           begin

piaocount<=piaocount+1'b1;

                 if(piaocount==5'b01010)

piaocount<=5'b00000;

else if(piaocount>=5'b00101)

                   begin

zheng<=1'b1;fan<=1'b0;

                   end

                 else

                    begin

zheng<=1'b0;fan<=1'b1;

                    end

            end

               

         end        

        

        s3:begin

led1<=1'b0;

led2<=1'b0;

led3<=1'b1;

led4<=1'b0;

piaocount<=5'b00000;

xicount<=5'b00000;

tuocount<=5'b00000;

           if(mod)

state<=s4;

               else 

state<=s3;

            begin

xicount<=xicount+1'b1;

                 if(xicount==5'b10100)

xicount<=5'b00000;

else if(xicount>=5'b01010)

                   begin

zheng<=1'b1;fan<=1'b0;

                   end

                 else

                    begin

zheng<=1'b0;fan<=1'b1;

                    end

            end

           end   

         

        s4:begin

led1<=1'b0;

led2<=1'b0;

led3<=1'b0;

led4<=1'b1;

piaocount<=5'b00000;

xicount<=5'b00000;

tuocount<=5'b00000;

           if(mod)

state<=s0;

               else 

state<=s4;

           begin

tuocount<=tuocount+1'b1;

                 if(tuocount==5'b00010)

tuocount<=5'b00000;

else if(tuocount>=4'b00001)

                   begin

zheng<=1'b1;fan<=1'b0;

                   end

                 else

                    begin

zheng<=1'b0;fan<=1'b1;

                    end

            end

               

         end   

        default:

                   begin

state<=s0;

                   end

    endcase

  end

endmodule

仿真图下载本文

显示全文
专题