1.实体框图
2.程序
library ieee;
use ieee.std_logic_11.all;
entity dff1 is
port(clk:in std_logic;
d:in std_logic;
clr:in std_logic;
set:in std_logic;
q:out std_logic);
end dff1;
architecture bhv of dff1 is
begin
process(clk,clr,set)
begin
if clr='0' then q<='0';
elsif CLK'EVENT AND CLK='0'
then
if set='1' then q<='1';
else q<=d;
end if;
end if;
end process;
end bhv;
3.仿真波形图
4.仿真波形分析
带同步清零和异步置数的D触发器
二、触发器的VHDL设计
1.实体框图
2.程序
library ieee;
use ieee.std_logic_11.all;
entity jk_ff is
port(j,k,clock,reset:in std_logic;
q,obar:out std_logic);
end entity jk_ff;
architecture one of jk_ff is
signal state:std_logic;
begin
po:process(clock,reset) is
begin
if (reset='1') then state<='0';
elsif rising_edge (clock)
then
case std_logic_vector'(j,k) is
when"11" => state <= not state;
when"10" => state <= '1';
when"01" => state <='0';
when others => null;
end case;
end if;
end process po;
q <= state;
obar <= not state;
end architecture one;
3.仿真波形图
4.仿真波形分析
带异步清零和同步置数的JK触发器下载本文
