PRELIMINARY
ML4800 Power Factor Correction and PWM Controller Combo
GENERAL DESCRIPTION
The ML4800 is a controller for power factor corrected, switched mode power supplies. Power Factor Correction (PFC) allows the use of smaller, lower cost bulk capacitors, reduces power line loading and stress on the switching FETs, and results in a power supply that fully complies with IEC1000-3-2 specification. Intended as a BiCMOS version of the industry-standard ML4824, the ML4800 includes circuits for the implementation of leading edge, average current, “boost” type power factor correction and a trailing edge, pulse width modulator (PWM). It also includes a TriFault Detect™ function to help ensure that no unsafe conditions will result from single component failure in the PFC. Gate-drivers with 1A capabilities minimize the need for external driver circuits. Low power requirements improve efficiency and reduce component costs.
An over-voltage comparator shuts down the PFC section in the event of a sudden decrease in load. The PFC section also includes peak current limiting and input voltage brownout protection. The PWM section can be operated in current or voltage mode, at up to 250kHz, and includes an accurate 50% duty cycle limit to prevent transformer saturation.FEATURES
I Internally synchronized leading-edge PFC and trailing-
edge PWM in one IC
I TriFault Detect™ for UL1950 compliance and
enhanced safety
I Slew rate enhanced transconductance error amplifier
for ultra-fast PFC response
I Low power: 200µA startup current, 5.5mA operating
current
I Low total harmonic distortion, high PF
I Reduced ripple current in storage capacitor between
PFC and PWM sections
I Average current, continuous boost leading edge PFC
I PWM configurable for current-mode or voltage mode
operation
I Current fed gain modulator for improved noise immunity
I Overvoltage and brown-out protection, UVLO, and soft
start
ML4800
PIN CONFIGURATION
PIN DESCRIPTION
PIN
NAME
FUNCTION
9DC I LIMIT PWM cycle-by-cycle current limit comparator input 10GND Ground
11PWM OUT PWM driver output 12PFC OUT PFC driver output 13V CC Positive supply
14V REF Buffered output for the internal 7.5V reference
15V FB PFC transconductance voltage error amplifier input
16
VEAO
PFC transconductance voltage error amplifier output
PIN
NAME
FUNCTION
1IEAO Slew rate enhanced PFC
transconductance error amplifier output 2I AC PFC AC line reference input to Gain Modulator
3I SENSE Current sense input to the PFC Gain Modulator
4V RMS PFC Gain Modulator RMS line voltage compensation input
5SS Connection point for the PWM soft start capacitor
6V DC PWM voltage feedback input 7RAMP 1Oscillator timing node; timing set by R T C T
8
RAMP 2
When in current mode, this pin functions as the current sense input;when in voltage mode, it is the PWM modulation ramp input.
1234
5678
161514131211109
IEAO I AC I SENSE V RMS SS V DC RAMP 1RAMP 2VEAO V FB V REF V CC PFC OUT PWM OUT GND DC I LIMIT
TOP VIEW
ML4800
16-Pin PDIP (P16)
16-Pin Narrow SOIC (S16N)
ML4800
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, V CC = 15V, R T = 52.3k Ω, C T = 470pF, T A = Operating Temperature Range (Note 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE ERROR AMPLIFIER
Input Voltage Range 05V Transconductance
V NON INV = V INV , VEAO = 3.75V
306590µ
Feedback Reference Voltage 2.43
2.5 2.57V Input Bias Current Note 2
-0.5-1.0
µA Output High Voltage 6.0
6.7V Output Low Voltage 0.10.4V Source Current V IN = ±0.5V, V OUT = 6V -40-140µA Sink Current V IN = ±0.5V, V OUT = 1.5V
40140µA Open Loop Gain
5060dB Power Supply Rejection Ratio
11V < V CC < 16.5V 50
60
dB
CURRENT ERROR AMPLIFIER
Input Voltage Range -1.52V Transconductance V NON INV = V INV , VEAO = 3.75V
50100150µ
Input Offset Voltage 0
415mV Input Bias Current -0.5-1.0
µA Output High Voltage 6.0
6.7V Output Low Voltage 0.65 1.0V Source Current V IN = ±0.5V, V OUT = 6V -40-104µA Sink Current V IN = ±0.5V, V OUT = 1.5V
40160µA Open Loop Gain
6070dB Power Supply Rejection Ratio
11V < V CC < 16.5V 6075
dB
OVP COMPARATOR
Threshold Voltage 2.65 2.75 2.85V Hysteresis
175
250
325
mV
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.
V CC ..............................................................................................18V I SENSE Voltage.................................................-5V to 0.7V Voltage on Any Other Pin......GND - 0.3V to V CCZ + 0.3V I REF ...........................................................................................10mA I AC Input Current....................................................10mA Peak PFC OUT Current, Source or Sink.......................1A Peak PWM OUT Current, Source or Sink ....................1A PFC OUT, PWM OUT Energy Per Cycle...................1.5µJ
Junction Temperature..............................................150°C Storage Temperature Range ......................-65°C to 150°C Lead Temperature (Soldering, 10 sec).....................260°C Thermal Resistance (θJA )
Plastic DIP ..........................................................80°C/W Plastic SOIC......................................................105°C/W
OPERATING CONDITIONS
Temperature Range
ML4800CX....................................................0°C to 70°C ML4800IX ..................................................-40°C to 85°C
Ω
Ω
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS TRI-FAULT DETECT
Fault Detect HIGH 2.65 2.75 2.85V
Time to Fault Detect HIGH V FB = V FAULT DETECT LOW to V FB=24ms
OPEN.470pF from V FB to GND
Fault Detect LOW0.40.50.6V PFC I LIMIT COMPARATOR
Threshold Voltage-0.9-1.0-1.1V
(PFC I LIMIT V TH - Gain Modulator Output)120220mV
Delay to Output150300ns DC I LIMIT COMPARATOR
Threshold Voltage0.95 1.0 1.05V
Input Bias Current±0.3±1µA
Delay to Output150300ns V IN OK COMPARATOR
Threshold Voltage 2.35 2.45 2.55V
Hysteresis0.8 1.0 1.2V GAIN MODULATOR
Gain (Note 3)I AC = 100µA, V RMS = V FB = 0V0.600.80 1.05
I AC = 50µA, V RMS = 1.2V, V FB = 0V 1.8 2.0 2.40
I AC = 50µA, V RMS = 1.8V, V FB = 0V0.85 1.0 1.25
I AC = 100µA, V RMS = 3.3V, V FB = 0V0.200.300.40
Bandwidth I AC = 100µA10MHz Output Voltage I AC = 350µA, V RMS = 1V,0.600.750.9V
V FB = 0V
OSCILLATOR
Initial Accuracy T A = 25°C717681kHz
Voltage Stability11V < V CC < 16.5V1%
Temperature Stability2%
Total Variation Line, Temp6884kHz
Ramp Valley to Peak Voltage 2.5V
PFC Dead Time250330ns
C T Discharge Current V RAMP 2 = 0V, V RAMP 1 = 2.5V 3.5 5.57.5mAML4800 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS REFERENCE
Output Voltage T A = 25°C, I(V REF) = 1mA7.47.57.6V
Line Regulation11V 0mA < I(V REF) < 5mA; T A = –40ºC to 85ºC1020mV Temperature Stability0.4% Total Variation Line, Load, Temp7.357.65V Long Term Stability T J = 125°C, 1000 Hours525mV PFC Minimum Duty Cycle V IEAO > 4.0V0% Maximum Duty Cycle V IEAO < 1.2V9095% Output Low Voltage I OUT = -20mA0.40.8V I OUT = -100mA0.7 2.0V I OUT = 10mA, V CC = 9V0.40.8V Output High Voltage I OUT = 20mA V CC – 0.8V V I OUT = 100mA V CC - 2V V Rise/Fall Time C L = 1000pF50ns PWM Duty Cycle Range0-440-470-49% Output Low Voltage I OUT = -20mA0.40.8V I OUT = -100mA0.7 2.0V I OUT = 10mA, V CC = 9V0.40.8V Output High Voltage I OUT = 20mA V CC – 0.8V V I OUT = 100mA V CC - 2V V Rise/Fall Time C L = 1000pF50ns SUPPLY Start-up Current V CC = 12V, C L = 0200350µA Operating Current14V, C L = 0 5.57mA Undervoltage Lockout Threshold12.41313.6V Undervoltage Lockout Hysteresis 2.5 2.8 3.1V Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: Includes all bias currents to other circuits connected to the V FB pin. Note 3: Gain = K x 5.3V; K = (I GAINMOD - I OFFSET) x [I AC (VEAO - 0.625)]-1; VEAO MAX=5V. ML4800 TYPICAL PERFORMANCE CHARACTERISTICS Voltage Error Amplifier (VEA) Transconductance (g m ) Current Error Amplifier (IEA) Transconductance (g m ) Gain Modulator Transfer Characteristic (K) 180160 140120100806040200T R A N S C O N D U C T A N C E (µ ) V FB (V) 5 3 Ω 1 4 2180160 140120100806040200T R A N S C O N D U C T A N C E (µ ) IEA INPUT VOLTAGE (mV) –500 500 Ω K I A IAC m V G AIN M O D = −×−8450625 µ2705.–1 V A R I A B L E G A I N B L O C K C O N S T A N T (K ) VRMS(V) 24 5 1 3 480 420360300240180120600 FUNCTIONAL DESCRIPTION The ML4800 consists of an average current controlled, continuous boost Power Factor Corrector (PFC) front end and a synchronized Pulse Width Modulator (PWM) back end. The PWM can be used in either current or voltage mode. In voltage mode, feedforward from the PFC output buss can be used to improve the PWM’s line regulation. In either mode, the PWM stage uses conventional trailing-edge duty cycle modulation, while the PFC uses leading-edge modulation. This patented leading/trailing edge modulation technique results in a higher usable PFC error amplifier bandwidth, and can significantly reduce the size of the PFC DC buss capacitor. The synchronization of the PWM with the PFC simplifies the PWM compensation due to the controlled ripple on the PFC output capacitor (the PWM input capacitor). The PWM section of the ML4800 runs at the same frequency as the PFC. In addition to power factor correction, a number of protection features have been built into the ML4800. These include soft-start, PFC overvoltage protection, peak current limiting, brownout protection, duty cycle limiting, and under-voltage lockout. POWER FACTOR CORRECTION Power factor correction makes a nonlinear load look like a resistive load to the AC line. For a resistor, the current drawn from the line is in phase with and proportional to the line voltage, so the power factor is unity (one). A common class of nonlinear load is the input of most power supplies, which use a bridge rectifier and capacitive input filter fed from the line. The peak-charging effect, which occurs on the input filter capacitor in these supplies, causes brief high-amplitude pulses of current to flow from the power line, rather than a sinusoidal current inphase with the line voltage. Such supplies present a power factor to the line of less than one (i.e. they cause significant current harmonics of the power line frequency to appear at their input). If the input current drawn by such a supply (or any other nonlinear load) can be made to follow the input voltage in instantaneous amplitude, it will appear resistive to the AC line and a unity power factor will be achieved. To hold the input current draw of a device drawing power from the AC line in phase with and proportional to the input voltage, a way must be found to prevent that device from loading the line except in proportion to the instantaneous line voltage. The PFC section of the ML4800 uses a boost-mode DC-DC converter to accomplish this. The input to the converter is the full wave rectified AC line voltage. No bulk filtering is applied following the bridge rectifier, so the input voltage to the boost converter ranges (at twice line frequency) from zero volts to the peak value of the AC input and back to zero. By forcing the boost converter to meet two simultaneous conditions, it is possible to ensure that the current drawn from the power line is proportional to the input line voltage. One of these conditions is that the output voltage of the boost converter must be set higher than the peak value of the line voltage. A commonly used value is 385VDC, to allow for a high line of 270VAC rms. The other condition is that the current drawn from the line at any given instant must be proportional to the line voltage. Establishing a suitable voltage control loop for the converter, which in turn drives a current error amplifier and switching output driver satisfies the first of these requirements. The second requirement is met by using the rectified AC line voltage to modulate the output of the voltage control loop. Such modulation causes the current error amplifier to command a power stage current that varies directly with the input voltage. In order to prevent ripple, which will necessarily appear at the output of the boost circuit (typically about 10VAC on a 385V DC level), from introducing distortion back through the voltage error amplifier, the bandwidth of the voltage loop is deliberately kept low. A final refinement is to adjust the overall gain of the PFC such to be proportional to 1/V IN2, which linearizes the transfer function of the system as the AC input voltage varies. Since the boost converter topology in the ML4800 PFC is of the current-averaging type, no slope compensation is required. PFC SECTION Gain Modulator Figure 1 shows a block diagram of the PFC section of the ML4800. The gain modulator is the heart of the PFC, as it is this circuit block which controls the response of the current loop to line voltage waveform and frequency, rms line voltage, and PFC output voltage. There are three inputs to the gain modulator. These are: 1)A current representing the instantaneous input voltage (amplitude and waveshape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is then fed into the gain modulator at I AC. Sampling current in this way minimizes ground noise, as is required in high power switching power conversion environments. The gain modulator responds linearly to this current. 2)A voltage proportional to the long-term RMS AC line voltage, derived from the rectified line voltage after scaling and filtering. This signal is presented to the gain modulator at V RMS. The gain modulator’s output is inversely proportional to V RMS2 (except at unusually low values of V RMS where special gain contouring takes over, to limit power dissipation of the circuit components under heavy brownout conditions). The relationship between V RMS and gain is called K, and is illustrated in the Typical Performance Characteristics. 3)The output of the voltage error amplifier, VEAO. The gain modulator responds linearly to variations in this voltage. Oscillator (RAMP 1) The oscillator frequency is determined by the values of R T and C T , which determine the ramp and off-time of the oscillator output clock:(2) The dead time of the oscillator is derived from the following equation: (3) at V REF = 7.5V: The dead time of the oscillator may be determined using:(4) The dead time is so small (tRAMP >> t DEADTIME ) that the operating frequency can typically be approximated by:(5) EXAMPLE: For the application circuit shown in the data sheet, with the oscillator running at:Solving for R T x C T yields 1.96 x 10-4. Selecting standard components values, C T = 390pF, and R T = 51.1k Ω.The dead time of the oscillator adds to the Maximum PWM Duty Cycle (it is an input to the Duty Cycle Limiter).With zero oscillator dead time, the Maximum PWM Duty Cycle is typically 45%. In many applications, care should be taken that C T not be made so large as to extend the Maximum Duty Cycle beyond 50%. This can be accomplished by using a stable 390pF capacitor for C T .PWM SECTION Pulse Width Modulator The PWM section of the ML4800 is straightforward, but there are several points which should be noted. Foremost among these is its inherent synchronization to the PFC section of the device, from which it also derives its basic timing. The PWM is capable of current-mode or voltage mode operation. In current-mode applications, the PWM ramp (RAMP 2) is usually derived directly from a current sensing resistor or current transformer in the primary of the output stage, and is thereby representative of the current flowing in the converter ’s output stage. DC I LIMIT ,which provides cycle-by-cycle current limiting, is typically connected to RAMP 2 in such applications. For voltage-mode operation or certain specialized applications, RAMP 2 can be connected to a separate RC timing network to generate a voltage ramp against which V DC will be compared. Under these conditions, the use of voltage feedforward from the PFC buss can assist in line regulation accuracy and response. As in current mode operation, the DC I LIMIT input would is used for output stage overcurrent protection. No voltage error amplifier is included in the PWM stage of the ML4800, as this function is generally performed on the output side of the PWM ’s isolation boundary. To facilitate the design of optocoupler feedback circuitry, an offset has been built into the PWM ’s RAMP 2 input which allows V DC to command a zero percent duty cycle for input voltages below 1.25V.PWM Current Limit The DC I LIMIT pin is a direct input to the cycle-by-cycle current limiter for the PWM section. Should the input voltage at this pin ever exceed 1V, the output of the PWM will be disabled until the output flip-flop is reset by the clock pulse at the start of the next PWM power cycle.V IN OK Comparator The V IN OK comparator monitors the DC output of the PFC and inhibits the PWM if this voltage on V FB is less than its nominal 2.45V. Once this voltage reaches 2.45V,which corresponds to the PFC output capacitor being charged to its rated boost voltage, the soft-start begins.PWM Control (RAMP 2) When the PWM section is used in current mode, RAMP 2is generally used as the sampling point for a voltage representing the current in the primary of the PWM ’s output transformer, derived either by a current sensing resistor or a current transformer. In voltage mode, it is the input for a ramp voltage generated by a second set of timing components (R RAMP2, C RAMP2), that will have a minimum value of zero volts and should have a peak value of approximately 5V. In voltage mode operation,feedforward from the PFC output buss is an excellent way to derive the timing ramp for the PWM stage.Soft Start Start-up of the PWM is controlled by the selection of the external capacitor at SS. A current source of 25µA supplies the charging current for the capacitor, and start-up of the PWM begins at 1.25V. Start-up delay can be programmed by the following equation: f t t OSC RAMP DEADTIME = +1 t C R In V V RAMP T T REF REF =××−−125375 ..t C R RAMP T T =××051 .t V mA C C DEADTIME T T = ×=×2555450..f t OSC RAMP = 1f kHz t OSC RAMP == 1001 ML4800 ML4800下载本文
