use IEEE.STD_LOGIC_11.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xianweiji is
Port ( clk : in std_logic; --50MHz标准脉冲;
clk_A, clk_B : in std_logic;--两个正弦波输入;
shift0,shift1 : out std_logic_vector(3 downto 0);--数码管位选信号;
led0, led1 : out std_logic_vector(7 downto 0));--数码管BCD码输出
end xianweiji;
architecture Behavioral of xianweiji is
signal sign : std_logic;
subtype word is std_logic_vector(3 downto 0);
type unit is array(6 downto 0) of word;
signal bcd : unit;
signal h0,h1,h2,h3 : std_logic_vector(3 downto 0);
signal numb, cda : integer range 0 to 499999;
signal y, yy : std_logic_vector(3 downto 0);
signal sss : std_logic_vector(3 downto 0);
signal x0,x1,x2,x3 : std_logic_vector(3 downto 0);
signal y0,y1,y2,y3 : std_logic_vector(3 downto 0);
signal cc : std_logic_vector(18 downto 0);
signal input0,input1:std_logic;
begin
process(clk)
variable b,d : std_logic;
begin
if clk'event and clk='1' then
if input0='1' and b='0' then b:='1'; numb<=conv_integer(cc);
cc<=(others=>'0');
elsif input0='0' and b='1' then b:='0';
if input1='1' and d='0' then d:='1'; cda<=conv_integer(cc);
if cc=49999999 then cc<=(others=>'0');
else cc<=cc+1;
end if;
elsif input1='0' and d='1' then d:='0';
if cc=49999999 then cc<=(others=>'0');
else cc<=cc+1;
end if;
else
if cc=49999999 then cc<=(others=>'0');
else cc<=cc+1;
end if;
end if;
else
if cc=49999999 then cc<=(others=>'0');
if input1='1' and d='0' then d:='1'; cda<=conv_integer(cc);
elsif input1='0' and d='1' then d:='0';
end if;
else cc<=cc+1;
if input1='1' and d='0' then d:='1'; cda<=conv_integer(cc);
elsif input1='0' and d='1' then d:='0';
end if;
end if;
end if;
end if;
end process;
process(clk)
variable count : integer range 0 to 19999;
variable count0 : integer range 0 to 2000000000;
variable sum : integer range 0 to 1800000000;
begin
if rising_edge(clk) then
if count=19999 then count:=0; count0:=0; h0<="0000"; h1<="0000";
h2<="0000"; h3<="0000"; sum:=cda*3600;
elsif count>=19990 then count:=count+1;
y0<=h0; y1<=h1; y2<=h2; y3<=h3;
elsif count<19990 then count:=count+1;
if count0 if h1="1001" then h1<="0000"; if h2="1001" then h2<="0000"; if h3="1001" then h3<="0000"; else h3<=h3+1; end if; else h2<=h2+1; end if; else h1<=h1+1; end if; else h0<=h0+1; end if; end if; end if; end if; end process; process(clk) variable count : integer range 0 to 19999999; variable aa : integer range 0 to 99999999; variable b : std_logic; begin if rising_edge(clk) then if count=19999999 then count:=0;bcd(6)<="0000"; bcd(5)<="0000"; bcd(4)<="0000"; bcd(3)<="0000"; bcd(2)<="0000"; bcd(1)<="0000"; bcd(0)<="0000"; elsif count>=19999990 then count:=count+1; aa:=0; if bcd(6)>"0000" then x3<=bcd(6); x2<=bcd(5); x1<=bcd(4); x0<=bcd(3); sss<="0001"; elsif bcd(5)>"0000" then x3<=bcd(5); x2<=bcd(4); x1<=bcd(3); x0<=bcd(2); sss<="0010"; elsif bcd(4)>"0000" then x3<=bcd(4); x2<=bcd(3); x1<=bcd(2); x0<=bcd(1); sss<="0100"; else x3<=bcd(3); x2<=bcd(2); x1<=bcd(1); x0<=bcd(0); sss<="1000"; end if; elsif count<19999990 then count:=count+1; if aa<49999999 then aa:=aa+numb; if bcd(0)="1001" then bcd(0)<="0000"; if bcd(1)="1001" then bcd(1)<="0000"; if bcd(2)="1001" then bcd(2)<="0000"; if bcd(3)="1001" then bcd(3)<="0000"; if bcd(4)="1001" then bcd(4)<="0000"; if bcd(5)="1001" then bcd(5)<="0000"; if bcd(6)="1001" then bcd(6)<="0000"; else bcd(6)<=bcd(6)+1; end if; else bcd(5)<=bcd(5)+1; end if; else bcd(4)<=bcd(4)+1; end if; else bcd(3)<=bcd(3)+1; end if; else bcd(2)<=bcd(2)+1; end if; else bcd(1)<=bcd(1)+1; end if; else bcd(0)<=bcd(0)+1; end if; end if; end if; end if; end process; process(clk) variable count : integer range 0 to 131071; --2^22; begin if rising_edge(clk) then if count<=32767 then count:=count+1; shift0<="0111"; shift1<="0111"; y<=y3; led0(0)<='1'; yy<=x3; if sss="1000" then led1(0)<='0'; else led1(0)<='1'; end if; elsif count<=65535 then count:=count+1; shift0<="1011"; shift1<="1011"; y<=y2; led0(0)<='1'; yy<=x2; if sss="0100" then led1(0)<='0'; else led1(0)<='1'; end if; elsif count<=98303 then count:=count+1; shift0<="1101"; shift1<="1101"; y<=y1; led0(0)<='0'; yy<=x1; if sss="0010" then led1(0)<='0'; else led1(0)<='1'; end if; elsif count<131071 then count:=count+1; shift0<="1110"; shift1<="1110"; y<=y0; led0(0)<='1'; yy<=x0; if sss="0001" then led1(0)<='0'; else led1(0)<='1'; end if; elsif count=131071 then count:=0; shift0<="1110"; shift1<="1110"; y<=y0; led0(0)<='1'; yy<=x0; if sss="0001" then led0(0)<='0'; else led0(0)<='1'; end if; end if; case yy is when "0000" => led1(7 downto 1)<="0000001"; when "0001" => led1(7 downto 1)<="1001111"; when "0010" => led1(7 downto 1)<="0010010"; when "0011" => led1(7 downto 1)<="0000110"; when "0100" => led1(7 downto 1)<="1001100"; when "0101" => led1(7 downto 1)<="0100100"; when "0110" => led1(7 downto 1)<="0100000"; when "0111" => led1(7 downto 1)<="0001111"; when "1000" => led1(7 downto 1)<="0000000"; when "1001" => led1(7 downto 1)<="0000100"; when others => led1(7 downto 1)<="0000001"; end case; case y is when "0000" => led0(7 downto 1)<="0000001"; when "0001" => led0(7 downto 1)<="1001111"; when "0010" => led0(7 downto 1)<="0010010"; when "0011" => led0(7 downto 1)<="0000110"; when "0100" => led0(7 downto 1)<="1001100"; when "0101" => led0(7 downto 1)<="0100100"; when "0110" => led0(7 downto 1)<="0100000"; when "0111" => led0(7 downto 1)<="0001111"; when "1000" => led0(7 downto 1)<="0000000"; when "1001" => led0(7 downto 1)<="0000100"; when others => led0(7 downto 1)<="0000001"; end case; end if; end process; end Behavioral;下载本文
