CH7025/CH7026

Advance Information

Chrontel

CH7025/CH7026 TV/VGA Encoder

Features

General Description

• TV encoder targets the handheld devices and other appropriate display devices used in consumer products. (i.e. automobile) • Support multiple output formats. Such as SDTV format (NTSC and PAL), HDTV format for 480p,576p,720p and 1080i,

analog RGB output for VGA. Sync signals can be provided in

separated or composite manner (programmable composite sync generation).

• Three on-chip 10-bit high speed DACs providing flexible output capabilities. Such as single, double or triple CVBS outputs, YPbPr output, RGB output and simultaneous CVBS and S-video outputs.

• 16Mbits SDRAM is used as frame buffer. Supporting for frame

rate conversion.

• Flexible up and down scaling engine is embedded including de-flickering capability.

• Programmable 24-bit/18-bit/16-bit/15-bit/12-bit/8-bit digital

input interface supports various RGB (RGB888, RGB666, RGB565 and etc), YCbCr (4:4:4 YCbCr, ITU656) and 2x or 3x multiplexed input. CPU interface are also supported.

• Support for flexible input resolution up to 800x800 and 1024x680.

• Pixel by pixel brightness, contrast, hue and saturation adjustment for each kind of output is supported. (For RGB output, only brightness and contrast adjustment is supported). • Pixel by pixel horizontal position adjustment and line by line vertical position adjustment are supported.

• 90/180/270 degree image rotation and vertical or horizontal flip functions are supported.

• Macrovision 7.1.L1 for SDTV is supported in CH7025. (CH7026 is Non-Macrovision part.)

• Macrovision TM copy protection support for progressive scan TV (480p, 576p CH7025 only)

• CGMS-A support for SDTV and HDTV

• TV/Monitor connection detect capability. DAC can be switched off based on detection result. (Driver support is required) • Programmable power management.

• Flexible pixel clock frequency from graphics controller is supported. (2.3MHz –120MHz) Flexible input clock from crystal or oscillator is supported. (2.3MHz – MHz) • Only slave mode supported.

• Offered in BGA or QFP package.

• Fully programmable through serial port.

• IO and SPC/SPD voltage supported is from 1.2V to 3.3V.

The CH7025/CH7026 is a device targeting handheld and similar systems which accept digital input signal, and encodes and transmits data through 10-bit DACs. The device is able to encode the video signals and generate synchronization

signals SDTV format for NTSC and PAL standards and HDTV format for 480p,576p,720p and 1080i. Analog RGB output and composite SYNC signal are also supported. The device accepts different data formats including RGB and

YCbCr (e.g. RGB565, RGB666, RGB888, ITU656 like YCbCr, etc.). 16Mbit SDRAM is embedded in

package. Frame rate conversion and Image rotation are possible. Note: the above feature list is subject to change without notice. Please contact Chrontel for more information and current updates.

TABLE OF CONTENTS

1.0Pin-out (5)

1.1Package Diagram (5)

1.2Pin Description (7)

2.0Functional Description (11)

2.1Input Interface (11)

2.1.1Overview (11)

2.1.2Input Clock and Data Timing Diagram (11)

2.1.3Input Data Voltage (12)

2.1.4Input Data Format (13)

2.2Chip Output (14)

2.2.1TV Output (14)

2.2.2VGA Output (15)

2.2.3Video DAC Output (15)

2.2.4DAC Single/Double Termination (15)

2.2.5TV Connection Detect (15)

2.2.6Picture Enhancement (15)

2.2.7Color Sub-carrier Generation (16)

2.2.8ITU-R BT.470 Compliance (16)

2.3Testing Functions (16)

2.3.1Test Pattern Select (16)

2.3.2SDRAM Power Down (17)

3.0Electrical Specifications (18)

3.1Absolute Maximum Rating (18)

3.2Recommended Operating Conditions (18)

3.3Electrical Characteristics (19)

3.4Digital Inputs / Outputs (19)

3.5AC Specifications (20)

4.0Package Dimensions (21)FIGURES AND TABLES

List of Figures

Figure 1: CH7025/CH7026 block diagram (2)

Figure 2: BGA Package (5)

Figure 3: 80 Pin LQFP Package (6)

Figure 4: Clock and Data Input Timing in 3x Multiplexed Mode (11)

Figure 5: SDR and DDR Input Data Formats (11)

Figure 6: Horizontal Input Timing (12)

Figure 7: Vertical Input Timing (12)

Figure 8: CPU Interface Timing (12)

Figure 9: 80 Pin BGA Package (21)

Figure 10: 80 Pin LQFP Package (22)

List of Tables

Table 1: Pin Name Description (BGA Package) (7)

Table 2: Pin Name Descriptions (LQFP80 Package) (9)

Table 3: Input Data Format (13)

Table 4: Supported SDTV Standards (14)

Table 5: Supported EDTV/HDTV Standards (14)

Table 6: Composite Sync Type (15)

Table 7: Video DAC Configurations for CH7025/CH7026 (15)

Table 8: Test Pattern Selection (16)

2.3.2SDRAM Power Down

Generally, SDRAM can have two kinds of power down modes. One is power down mode, the other is deep power down mode. For power down mode, by dropping the CKE signal from high to low and holding CS signal high, then SDRAM goes into the power down mode. All data contents will be held in the bank. For deep power down mode, a command is required to issued. There is a bit called MEMPD in register map. It can be used to enable the deep power mode. During deep power mode, all the data in memory banks will be lost, and the SDRAM leakage current is less than 1uA. An very important thing required to be noted here is that not all the SDRAM parts support either power down or deep power down mode. In these cases, even CH7025/CH7026 enters into power down, the leakage current is still large ( >100uA ). This current is primarily derived from the SDRAM die.

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Figure 10: 80 Pin LQFP Package下载本文