LIBRARY IEEE;
USE IEEE.STD_LOGIC_11.ALL;
ENTITY CHK IS
PORT(DIN:IN STD_LOGIC;
CLK,CLR:IN STD_LOGIC;
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
AB:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END CHK;
ARCHITECTURE ART OF CHK IS
SIGNAL Q :INTEGER RANGE 0 TO 8;
BEGIN
PROCESS ( CLK,CLR )
BEGIN
IF CLR= '1' THEN Q<=0;
ELSIF CLK'EVENT AND CLK= '1' THEN
CASE Q IS
WHEN 0 => IF DIN =D(7) THEN Q<= 1 ;ELSE
Q<=0;END IF;
WHEN 1 => IF DIN =D(6) THEN Q<= 2 ;ELSE
Q<=0;END IF;
WHEN 2 => IF DIN =D(5) THEN Q<= 3 ;ELSE
Q<=0;END IF;
WHEN 3=> IF DIN =D(4) THEN Q<= 4 ;ELSE
Q<=0;END IF;
WHEN 4 => IF DIN =D(3) THEN Q<= 5 ;ELSE
Q<=0;END IF;
WHEN 5 => IF DIN =D(2) THEN Q<= 6 ;ELSE
Q<=0;END IF;
WHEN 6 => IF DIN =D(1) THEN Q<= 7 ;ELSE
Q<=0;END IF;
WHEN 7 => IF DIN =D(0) THEN Q<= 8 ;ELSE
Q<=0;END IF;
WHEN OTHERS => Q<=0;
END CASE;
END IF ;
END PROCESS;
PROCESS(Q)
BEGIN
IF Q= 8 THEN AB<= "1010";
ELSE AB<= "1011";
END case;
END IF ;
END PROCESS;
END behave;
2、实验结果：下载本文
