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FEATURES DESCRIPTION
APPLICATIONS
function diagram
(positive logic)
V CC V ref
R
SN65HVD251-Q1
SLLS788–APRIL2007
CAN TRANSCEIVER
•Qualified for Automotive Applications The SN65HVD251is intended for use in applications
employing the Controller Area Network(CAN)serial •Drop-In Improved Replacement for the
communication physical layer in accordance with the PCA82C250and PCA82C251
ISO118Standard.The SN65HVD251provides •Bus-Fault Protection of±36V
differential transmit capability to the bus and •Meets or Exceeds ISO118differential receive capability to a CAN controller at
speeds up to1megabit per second(Mbps).•Signaling Rates(1)up to1Mbps
•High Input Impedance Allows up to120Designed for operation in harsh environments,the SN65HVD251Nodes on a Bus device features crosswire,overvoltage,and loss of
ground protection to±36V.Also featured are •Bus Pins ESD Protection Exceeds9kV(HBM)
overtemperature protection as well as–7-V to12-V •Unpowered Node Does Not Disturb the Bus common-mode range,and tolerance to transients of
•Low-Current Standby Mode:200μA Typical±200V.The transceiver interfaces the single-ended
CAN controller with the differential CAN bus found in •Thermal Shutdown Protection
industrial,building automation,and automotive •Glitch-Free Power-Up and Power-Down Bus applications.
Protection for Hot Plugging
Rs,pin8,selects one of three different modes of •DeviceNet™Vendor ID#806
operation:high-speed,slope control,or low-power (1)The signaling rate of a line is the number of voltage mode.The high-speed mode of operation is selected
transitions that are made per second expressed in bps(bits by connecting pin8to ground,allowing the per second).
transmitter output transistors to switch as fast as
possible with no limitation on the rise and fall slope.
The rise and fall slope can be adjusted by •CAN Data Buses connecting a resistor to ground at pin8;the slope is •Industrial Automation proportional to the pin's output current.Slope control
with an external resistor value of10kΩgives –DeviceNet Data Buses
~15V/μs slew rate;100kΩgives~2V/μs slew rate.
–Smart Distributed Systems(SDS™)
If a high logic level is applied to the Rs pin8,the •SAE J1939Standard Data Bus Interface
device enters a low-current standby mode where the •NMEA2000Standard Data Bus Interface
driver is switched off and the receiver remains active.•ISO11783Standard Data Bus Interface The local protocol controller returns the device to the
normal mode when it transmits to the bus.
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.Copyright©2007,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas
Instruments standard warranty.Production processing does not
necessarily include testing of all parameters.
www.ti.com ABSOLUTE MAXIMUM RATINGS
ABSOLUTE MAXIMUM POWER DISSIPATION RATINGS
SN65HVD251-Q1
SLLS788–APRIL2007
These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)
PART NUMBER PACKAGE MARKED AS SN65HVD251QDRQ18-pin SOIC(Tape and Reel)251Q1
(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI
web site at www.ti.com.
over operating free-air temperature range(unless otherwise noted)(1)(2)
SN65HVD251
Supply voltage range,V CC–0.3V to7V
Voltage range at any bus terminal CANH,CANL–36V to36V Transient voltage per ISO7637,pulse1,2,3a,3b CANH,CANL±200V
Input voltage range,V I D,Rs,R–0.3V to V CC+0.5 Receiver output current,I O–10mA to10mA
CANH,CANL,GND9kV
Human-Body Model(3)
All pins6kV
Electrostatic discharge
Charged-Device Model(4)All pins1kV
Machine Model All pins200V
Continuous total power dissipation See Dissipation Rating Table (1)Stresses beyond those listed under"absolute maximum ratings"may cause permanent damage to the device.These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)All voltage values,except differential I/O bus voltages,are with respect to network ground terminal.
(3)Tested in accordance with JEDEC Standard22,Test Method A114-A
(4)Tested in accordance with JEDEC Standard22,Test Method C101
CIRCUIT BOARD T A=25°C DERATING FACTOR(1)T A=85°C POWER T A=125°C POWER PACKAGE
MODEL POWER RATING ABOVE T A=25°C RATING RATING
Low-K(2)576mW 4.8mW/°C288mW96mW SOIC(D)
High-K(3)924mW7.7mW/°C462mW154mW
(1)This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2)In accordance with the Low-K thermal metric definitions of EIA/JESD51-3
(3)In accordance with the High-K thermal metric definitions of EIA/JESD51-7
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THERMAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS SN65HVD251-Q1 SLLS788–APRIL2007
PARAMETER TEST CONDITIONS VALUE UNIT
MIN TYP MAX
θJB Junction-to-board thermal resistance78.7°C/W
θJC Junction-to-case thermal resistance44.6°C/W
V CC=5V,T J=27°C,R L=60Ω,
R S at0V,Input to D a500-kHz97.7mW
50%duty cycle square wave
P D Device power dissipation
V CC=5.5V,T J=130°C,R L=60Ω,
R S at0V,Input to D a500-kHz50%142mW
duty cycle square wave
T SD Thermal shutdown junction temperature165°C
over recommended operating conditions(unless otherwise noted)
PARAMETER MIN NOM MAX UNIT Supply voltage,V CC 4.5 5.5V Voltage at any bus terminal(separately or common mode)V I or V IC–7(1)12V High-level input voltage,V IH D input0.7V CC V Low-level input voltage,V IL D input0.3V CC V Differential input voltage,V ID–66V Input voltage to Rs,V I(Rs)0V CC V Input voltage at Rs for standby,V I(Rs)0.75V CC V CC V
Rs wave-shaping resistance0100kΩ
Driver–50
High-level output current,I OH mA
Receiver–4
Driver50
Low-level output current,I OL mA
Receiver4 Operating free-air temperature,T A–40125°C Junction temperature,T j145°C (1)The algebraic convention,in which the least positive(most negative)limit is designated as minimum is used in this data sheet.
3
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DRIVER ELECTRICAL CHARACTERISTICS
DRIVER SWITCHING CHARACTERISTICS
SN65HVD251-Q1
SLLS788–APRIL 2007
over recommended operating conditions (unless otherwise noted)
(1)
All typical values are at 25°C and with a 5-V supply.
over recommended operating conditions (unless otherwise noted)
4
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RECEIVER ELECTRICAL CHARACTERISTICS
RECEIVER SWITCHING CHARACTERISTICS
VREF PIN CHARACTERISTICS
SN65HVD251-Q1
SLLS788–APRIL 2007
over
recommended operating conditions (unless otherwise noted)
over recommended operating conditions (unless otherwise noted)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN MAX UNIT –5μA Reference output voltage
V
–50μA 0.4V CC
0.6V CC
5
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DEVICE SWITCHING CHARACTERISTICS
SN65HVD251-Q1
SLLS788–APRIL 2007
over recommended operating conditions
(unless otherwise noted)
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PARAMETER MEASUREMENT INFORMATION
I I
93.5 V
Recessive
Dominant
O (CANH)
V O (CANL)
V 92.5 V
91.5 V
V I
–7 V 3 V TEST 3 12 V
Figure 1.Driver Voltage,Current,and Test Definition
Figure 2.Bus Logic State Voltage Definitions
Figure 3.Driver V OD
V CC
V O(D)O(R)
V IC
=
O
V OH
V OL
Figure 4.Driver Test Circuit and Voltage Waveforms
Figure 5.Receiver Voltage and Current Definitions
A.The input pulse is supplied by a generator having the following characteristics:PRR ≤125kHz,50%duty cycle,t r ≤6ns,t f ≤6ns,Z O =50Ω.
B.
C L includes instrumentation and fixture capacitance within ±20%.
Figure 6.Receiver Test Circuit and Voltage Waveforms
CC
Pulse Generator 15 m s Duration 1% Duty Cycle t r , t r 3 100 ns
0 V 60 W + 1%
V CC V OH
V OL
0.3 V CC A.This test is conducted to test survivability only.Data stability at the R output is not specified.
Figure 7.Test Circuit,Transient Overvoltage Test
Table 1.Receiver Characteristics Over Common Mode Voltage
INPUT
MEASURED
OUTPUT
V CANH V CANL |V ID |R
12V 11.1V 900mV L –6.1V –7V 900mV L V OL
–1V –7V 6V L 12V 6V 6V L –6.5V –7V 500mV H 12V 11.5V 500mV H –7V –1V 6V H V OH
6V 12V 6V H open
open
X
H
Figure 8.t en Test Circuit and Voltage Waveforms
+20%
V OC(PP)
V I
W+ 1%
V CC
0 V
V OH
V OL
D Input
R Output
A.The input pulse is supplied by a generator having the following characteristics:PRR≤125kHz,50%duty cycle,
t r≤6ns,t f≤6ns,Z O=50Ω.
Figure9.Peak-to-Peak Common Mode Output Voltage
Figure10.t LOOP Test Circuit and Voltage Waveforms
0 V
–7 V or 12 V
I OS(SS)J
0 V or V CC
OH
OL
Figure 11.Driver Short-Circuit Test
A.The input pulse is supplied by a generator having the following characteristics:PRR ≤125kHz,50%duty cycle,t r ≤6ns,t f ≤6ns,Z O =50Ω.
B.
C L includes instrumentation and fixture capacitance within ±20%.
Figure 12.Receiver Propagation Delay in Standby Test Circuit and Waveforms
DEVICE INFORMATION
500 mV 900 mV
R1R212 V
I
V ID 50 W 50 W
450 W 227 W
FUNCTION TABLES
A.
All input pulses are supplied by a generator having the following characteristics:f <1.5MHz,T A =25°C,V CC =5V.
Figure 13.Common-Mode Input Voltage Rejection Test
Table 2.DRIVER
INPUTS OUTPUTS
Voltage at R s ,V Rs
BUS STATE D CANH CANL L V Rs <1.2V H L Dominant H V Rs <1.2V
Z Z Recessive Open X
Z Z Recessive X
V Rs >0.75V CC
Z
Z
Recessive
Table 3.RECEIVER
DIFFERENTIAL INPUTS [V ID =V(CANH)–V(CANL)]
OUTPUT R (1)
V ID ≥0.9V L 0.5V (1) H =high level;L =low level;X =irrelevant;?=indeterminate;Z =high impedance www.ti.com SN65HVD251-Q1 SLLS788–APRIL 2007 Figure 14.Equivalent Input and Output Schematic Diagrams 13 Submit Documentation Feedback www.ti.com TYPICAL CHARACTERISTICS t L O O P 1 – L o o p T i m e – n s T A – Free-Air Temperature –5 C t L O O P 2 – L o o p T i m e – n s T A – Free-Air Temperature – 5C I C C – R M S S u p p l y C u r r e n t –m A Signaling Rate – kbps 0 1020304050607080012345I O H – D r i v e r H i g h -L e v e l O u t p u t C u r r e n t –m A V O CANH – High-Level Output Voltage – V I O L – D r i v e r L o w -L e v e l O u t p u t C u r r e n t –m A V O CANL – Low-Level Output Voltage – V 00.511.522.53–55–400257085125V O D (D ) – D o m i n a n t D i f f e r e n t i a l O u t p u t V o l t a g e – V T A – Free-Air Temperature –5 C 0102030405060I O – D r i v e r O u t p u t C u r r e n t –m A V CC – Supply Voltage – V 0102030405060708090100 t f - D i f f e r e n t i a l O u t p u t F a l l T i m e -n s R S - Slope Resistance - k W −3 −2.50−2−1.50−1−0.500−50050100150T A − Free-Air Temperature − °C I n p u t R e s i s t a n c e M a t c h i n g − %SN65HVD251-Q1SLLS788–APRIL 2007t LOOP1–LOOP TIME t LOOP2–LOOP TIME SUPPLY CURRENT (RMS)vs vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE SIGNALING RATE Figure 15. Figure 16.Figure 17.DRIVER LOW-LEVEL OUTPUT DRIVER HIGH-LEVEL OUTPUT DOMINANT DIFFERENTIAL CURRENT CURRENT OUTPUT VOLTAGE vs vs vs LOW-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE FREE-AIR TEMPERATURE Figure 18.Figure 19. Figure 20.DIFFERENTIAL OUTPUT DRIVER OUTPUT CURRENT FALL TIME INPUT RESISTANCE MATCHING vs vs vs SUPPLY VOLTAGE SLOPE RESISTANCE (Rs) FREE-AIR TEMPERATURE Figure 21.Figure 22.Figure 23. 14Submit Documentation Feedback www.ti.com APPLICATION INFORMATION 500 mV Threshold 900 mV Threshold ALLOWABLE JITTER NOISE MARGIN NOISE MARGIN RECEIVER DETECTION WINDOW 75% SAMPLE POINT SN65HVD251-Q1SLLS788–APRIL 2007 oscillators in a system must also be accounted for The basics of bus arbitration require that the receiver with adjustments in signaling rate and stub and bus at the sending node designate the first bit as length.Table 4lists the maximum signaling rates dominant or recessive after the initial wave of the SN65HVD251in high-speed mode first bit of a message travels to the most remote with several bus lengths of category 5,shielded node on a network and back again.Typically,this twisted-pair (CAT 5STP)cable.sample is made at 75%of the bit width,and within this limitation,the maximum allowable signal Table 4.Maximum Signaling Rates for Various distortion in a CAN network is determined by network Cable Lengths electrical parameters. BUS LENGTH (m)SIGNALING RATE (kbps)Factors to be considered in network design include 301000the 5ns/m propagation delay of typical twisted-pair 100500bus cable;signal amplitude loss due to the loss 250250mechanisms of the cable;and the number,length, and spacing of drop-lines (stubs)on a network. 500 125Under strict analysis,variations among the different 100062.5 The ISO 118standard specifies a maximum bus length of 40m and maximum stub length of 0.3m with a maximum of 30nodes.However,with careful design,users can have longer cables,longer stub lengths,and many more nodes on a bus.(Note:Non-standard application may come with a trade-off in signaling rate.)A bus with a large number of nodes requires a transceiver with high input impedance such as the HVD251. The Standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded)with 120-Ωcharacteristic impedance (Zo).Resistors equal to the characteristic impedance of the line terminate both ends of the cable to prevent signal reflections.Unterminated drop-lines connect nodes to the bus and should be kept as short as possible to minimize signal reflections. Connectors,while not specified by the ISO 118standard,should have as little effect as possible on standard operating parameters such as capacitive loading.Although unshielded cable is used in many applications,data transmission circuits employing CAN transceivers are usually used in applications requiring a rugged interconnection with a wide common-mode voltage range.Therefore,shielded cable is recommended in these electronically harsh environments,and when coupled with the –2-V to 7-V common-mode range of tolerable ground noise specified in the standard,helps to ensure data integrity.The HVD251extends data integrity beyond that of the standard with an extended –7-V to 12-V range of common-mode operation. Figure 24.Typical CAN Differential Signal Eye Pattern 15Submit Documentation Feedback www.ti.com Typical Application 120W W SN65HVD251-Q1SLLS788–APRIL 2007An eye pattern is a useful tool for measuring overall signal quality.As displayed in Figure 24,the differential signal changes logic states in two places on the display,producing an eye .Instead only one logic crossing on the scope,an entire bit of data is brought into view.The resulting eye pattern includes all effects of systemic and random distortion,and displays the time during which a signal may be considered valid. The height of the eye above or below the receiver threshold voltage level at the sampling point is the noise margin of the system.Jitter is typically measured at the differential voltage zero-crossing during the logic state transition of a signal.Note that jitter present at the receiver threshold voltage level is considered by some to be a more effective representation of the jitter at the input of a receiver. As the sum of skew and noise increases,the eye closes and data is corrupted.Closing the width decreases the time available for accurate sampling,and lowering the height enters the 900mV or 500mV threshold of a receiver. Different sources induce noise onto a signal.The more obvious noise sources are the components of a transmission circuit themselves;the signal transmitter,traces and cables,connectors,and the receiver.Beyond that,there is a termination dependency,cross-talk from clock traces and other proximity effects,V CC and ground bounce,and electromagnetic interference from nearby electrical equipment. The balanced receiver inputs of the HVD251mitigate most sources of signal corruption,and when used with a quality shielded twisted-pair cable,help ensure data integrity. Figure 25.Typical HVD251Application 16Submit Documentation Feedback PACKAGING INFORMATION Orderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)SN65HVD251QDRQ1 ACTIVE SOIC D 82500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE:Product device recommended for new designs. LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect. NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design. PREVIEW:Device has been announced but is not in production.Samples may or may not be available. OBSOLETE:TI has discontinued the production of the device. (2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD:The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above. Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material) (3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature. 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