128MbSDRAMx32_1.fm -Rev. J 6/06 EN

©2001 Micron Technology, Inc. All rights reserved.

Synchronous DRAM

MT48LC4M32B2 – 1 Meg x 32 x 4 banks

For the latest data sheet, please refer to the Micron Web site: www.micron.com/sdram

Features •PC100 functionality

•Fully synchronous; all signals registered on positive edge of system clock

•Internal pipelined operation; column address can be changed every clock cycle

•Internal banks for hiding row access/precharge •Programmable burst lengths: 1, 2, 4, 8, or full page •Auto precharge, includes concurrent auto precharge, and auto refresh modes •Self Refresh Mode

•ms, 4,096-cycle refresh (15.6µs/row)•LVTTL-compatible inputs and outputs •Single +3.3V ±0.3V power supply

•Supports CAS latency (CL) of 1, 2, and 3

Notes:1.Off-center parting line Options

Marking

•Configuration

–4 Meg x 32 (1 Meg x 32 x 4 banks)4M32B2•Package –

OCPL 1

–86-pin TSOP (400 mil)

TG –86-pin TSOP (400 mil) lead-free P –90-ball FBGA (8mm x 13mm)

F5–90-ball FBGA (8mm x 13mm) lead-free B5•Timing (cycle time)–6ns (166 MHz)-6–7ns (143 MHz)-7•Die

revision

:G •Operating temperature range –Commercial (0° to +70°C)None –Extended (–40°C to +85°C)IT

Table 1:

Key Timing Parameters

CL = CAS (READ) latency

Speed Grade Clock Frequency Access Time

Setup Time Hold Time Cl = 3-6166 MHz 5.5ns 1.5ns 1ns -7

143 MHz

5.5ns

2ns

1ns

Figure 1:

Pin Assignment (Top View) 86-Pin TSOP

Part Number Example:

MT48LC4M32B2TG-7:G

Table 2:

Configurations

4 Meg x 32

Configuration 1 Meg x 32 x 4 banks

Refresh count 4K

Row addressing 4K (A0–A11)Bank addressing 4 (BA0, BA1)Column addressing 256 (A0–A7)

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Burst Length (BL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Write Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 COMMAND INHIBIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 NO OPERATION (NOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 ACTIVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 BURST TERMINATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 AUTO REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 SELF REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 BANK/ROW ACTIVATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 READs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 WRITEs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Clock Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Burst READ/Single WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Temperature and Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65List of Figures

Figure 1:Pin Assignment (Top View) 86-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 2:Functional Block Diagram 4 Meg x 32 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Figure 3:90-Ball FBGA Pin Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Figure 4:Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Figure 5:CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 6:Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Figure 7:Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 8:READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Figure 9:CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Figure 10:Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 11:Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Figure 12:READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Figure 13:READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Figure 14:READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Figure 15:Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Figure 16:WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Figure 17:WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 18:WRITE-to0WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 19:Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Figure 20:WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Figure 21:WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Figure 22:Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Figure 23:PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Figure 24:Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Figure 25:CLOCK SUSPEND During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Figure 26:CLOCK SUSPEND During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Figure 27:READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Figure 28:READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Figure 29:WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Figure 30:WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Figure 31:Example Temperature Test Point Location, 54-Pin TSOP: Top View . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Figure 32:Example Temperature Test Point Location, 90-Ball VFBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . .43 Figure 33:Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Figure 34:Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Figure 35:Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Figure 36:Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Figure 37:Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Figure 38:Single READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Figure 39:Read – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Figure 40:Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Figure 41:Read – Full-page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Figure 42:Read – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Figure 43:Single Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Figure 44:Write – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Figure 45:Write – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Figure 46:Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Figure 47:Write – Full-page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Figure 48:Write – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 49:86-Pin Plastic TSOP (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Figure 50:90-Ball FBGA (8mm x 13mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66List of Tables

Table 1:Key Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 2:Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Table 3:128Mb (x32) SDRAM Part Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 4:Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Table 5:Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Table 6:Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 7:CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 8:Truth Table–Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 9:Truth Table – CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Table 10:Truth Table – Current State Bank n, Command To Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Table 11:Truth Table – CURRENT STATE BANK n, COMMAND TO BANK m. . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 12:Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 13:Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Table 14:Thermal Impedance Simulated Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Table 15:DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 16:I DD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 17:Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Table 18:Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .45 Table 19:AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46Table 3: 128Mb (x32) SDRAM Part Number

Part Number Architecture

MT48LC4M32B2TG 4 Meg x 32

MT48LC4M32B2P 4 Meg x 32

MT48LC4M32B2F5 4 Meg x 32

MT48LC4M32B2B5 4 Meg x 32

General Description

The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing

134,217,728-bits. It is internally configured as a quad-bank DRAM with a synchronous

interface (all signals are registered on the positive edge of the clock signal, CLK). Each of

the 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select

the bank, A0–A11 select the row). The address bits registered coincident with the READ

or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8

locations, or the full page, with a burst terminate option. An auto precharge function

may be enabled to provide a self-timed row precharge that is initiated at the end of the

burst sequence.

The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed oper-

ation. This architecture is compatible with the 2n rule of prefetch architectures, but it

also allows the column address to be changed on every clock cycle to achieve a high-

speed, fully random access. Precharging one bank while accessing one of the other three

banks will hide the precharge cycles and provide seamless, high-speed, random-access

operation.

The 128Mb SDRAM is designed to operate in 3.3V, low-power memory systems. An auto

refresh mode is provided, along with a power-saving, power-down mode. All inputs and

outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating performance, including the

ability to synchronously burst data at a high data rate with automatic column-address

generation, the ability to interleave between internal banks to hide precharge time and

the capability to randomly change column addresses on each clock cycle during a burst

access.Figure 2: Functional Block Diagram 4 Meg x 32 SDRAM

Ball Assignments and Descriptions Figure 3: 90-Ball FBGA Pin Assignment (Top View)

Table 4: Pin Descriptions

Pin Numbers Symbol Type Description

68CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled

on the positive edge of CLK. CLK also increments the internal burst counter

and controls the output registers.

67CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.

Deactivating the clock provides precharge power-down and SELF REFRESH

operation (all banks idle), active power-down (row active in any bank) or

CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous

except after the device enters power-down and self refresh modes, where CKE

becomes asynchronous until after exiting the same mode. The input buffers,

including CLK, are disabled during power-down and self refresh modes,

providing low standby power. CKE may be tied HIGH.

20CS#Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH,

but READ/WRITE bursts already in progress will continue and DQM operation

will retain its DQ mask capability while CS# is HIGH. CS# provides for external

bank selection on systems with multiple banks. CS# is considered part of the

command code.

17, 18, 19WE#,

CAS#,

RAS#Input Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the command being entered.

16, 71, 28, 59DQM0–

DQM3Input Input/Output mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked

during a WRITE cycle. The output buffers are placed in a High-Z state (two-

clock latency) during a READ cycle. DQM0 corresponds to DQ0–DQ7, DQM1

corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3

corresponds to DQ24–DQ31. DQM0–DQM3 are considered same state when

referenced as DQM.

22, 23BA0, BA1Input Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ,

WRITE, or PRECHARGE command is being applied.

25–27, 60–66, 24,

21A0–A11 Input Address inputs: A0–A11 are sampled during the ACTIVE command (row-

address A0–A10) and READ/WRITE command (column-address A0–A7 with A10

defining auto precharge) to select one location out of the memory array in the

respective bank. A10 is sampled during a PRECHARGE command to determine

if all banks are to be precharged (A10 [HIGH]) or bank selected by BA0, BA1

(LOW). The address inputs also provide the op-code during a LOAD MODE

REGISTER command.

2, 4, 5, 7, 8, 10, 11, 13, 74, 76, 77, 79, 80, 82, 83, 85, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56 DQ0–

DQ31

Input/

Output

Data I/Os: Data bus.

14, 30, 57, 69, 70,

73NC–No connect: These pins should be left unconnected. Pin 70 is reserved for SSTL reference voltage supply.

3, 9, 35, 41, 49, 55,

75, 81

V DD Q Supply DQ power supply: Isolated on the die for improved noise immunity.

6, 12, 32, 38, 46,

52, 78, 84

V SS Q Supply DQ ground: Provide isolated ground to DQs for improved noise immunity.

1, 15, 29, 43V DD Supply Power supply: +3.3V ±0.3V.

44, 58, 72, 86V SS Supply Ground.Table 5: Ball Descriptions

90-Ball FBGA Symbol Type Description

J1CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled

on the positive edge of CLK. CLK also increments the internal burst counter

and controls the output registers.

J2CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.

Deactivating the clock provides precharge power-down and SELF REFRESH

operation (all banks idle), active power-down (row active in any bank) or

CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous

except after the device enters power-down and self refresh modes, where CKE

becomes asynchronous until after exiting the same mode. The input buffers,

including CLK, are disabled during power-down and self refresh modes,

providing low standby power. CKE may be tied HIGH.

J8CS#Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH,

but READ/WRITE bursts already in progress will continue and DQM operation

will retain its DQ mask capability while CS# is HIGH. CS# provides for external

bank selection on systems with multiple banks. CS# is considered part of the

command code.

J9, K7, K8RAS#,

CAS#,

WE#Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered.

K9, K1, F8, F2DQM0–3Input Input/Output mask: DQM is sampled HIGH and is an input mask signal for write

accesses and an output enable signal for read accesses. Input data is masked

during a WRITE cycle. The output buffers are placed in a High-Z state (two-

clock latency) when during a READ cycle. DQM0 corresponds to DQ0–DQ7,

DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and

DQM3 corresponds to DQ24–DQ31. DQM0–3 are considered same state when

referenced as DQM.

J7, H8BA0, BA1Input Bank address input(s): BA0 and BA1 define to which bank the ACTIVE, READ,

WRITE or PRECHARGE command is being applied. These pins also provide the

op-code during a LOAD MODE REGISTER command.

G8, G9, F7, F3, G1, G2, G3, H1, H2, J3,

G7, H9A0–A11Input Address inputs: A0–A11 are sampled during the ACTIVE command (row-

address A0–A11) and READ/WRITE command (column-address A0–A7; with A10

defining auto precharge) to select one location out of the memory array in the

respective bank. A10 is sampled during a PRECHARGE command to determine

if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1

(LOW). The address inputs also provide the op-code during a LOAD MODE

REGISTER command.

R8, N7, R9, N8, P9, M8, M7, L8, L2, M3, M2, P1, N2, R1, N3, R2, E8, D7, D8, B9, C8, A9, C7, A8, A2, C3, A1, C2, B1, D2, D3, E2DQ0–

DQ31

I/O Data input/output: Data bus

E3, E7, H3, H7, K2,

K3NC–No connect: These pins should be left unconnected. H7 is a not connect for this part but may be used as A12 in future designs.

B2, B7, C9, D9, E1,

L1, M9, N9, P2, P7

V DD Q Supply DQ power: Provide isolated power to DQs for improved noise immunity.

B8, B3, C1, D1, E9,

L9, M1, N1, P3, P8

V SS Q Supply DQ ground: Provide isolated ground to DQs for improved noise immunity.

A7, F9, L7, R7V DD Supply Power supply: Voltage dependant on option.

A3, F1, L3, R3V SS Supply Ground.128Mb: x32 SDRAM

Functional Description Functional Description

In general, this 128Mb SDRAM (1 Meg x 32 x 4 banks) is a quad-bank DRAM that oper-

ates at 3.3V and includes a synchronous interface (all signals are registered on the posi-

tive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096

rows by 256 columns by 32-bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1

select the bank, A0–A11 select the row). The address bits (A0–A7) registered coincident

with the READ or WRITE command are used to select the starting column location for

the burst access.

Prior to normal operation, the SDRAM must be initialized. The following sections

provide detailed information covering device initialization, register definition,

command descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a predefined manner. Operational

procedures other than those specified may result in undefined operation. Once power is

applied to V DD and V DD Q (simultaneously) and the clock is stable (stable clock is

defined as a signal cycling within timing constraints specified for the clock pin), the

SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND

INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least

through the end of this period, COMMAND INHIBIT or NOP commands must be

applied.

Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP

command having been applied, a PRECHARGE command should be applied. All banks

must then be precharged, thereby placing the device in the all banks idle state.

Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the

AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-

ming. Because the mode register will power up in an unknown state, it must be loaded

prior to applying any operational command. If desired, the two AUTO REFRESH

commands can be issued after the LMR command.

The recommended power-up sequence for SDRAMs:

1.Simultaneously apply power to V DD and V DD Q.

2.Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-

compatible.

3.Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing

constraints specified for the clock pin.

4.Wait at least 100µs prior to issuing any command other than a COMMAND INHIBIT

or NOP.

5.Starting at some point during this 100µs period, bring CKE HIGH. Continuing at least

through the end of this period, 1 or more COMMAND INHIBIT or NOP commands

must be applied.

6.Perform a PRECHARGE ALL command.7.Wait at least t RP time, during this time NOPs or DESELECT commands must be given.

All banks will complete their precharge, thereby placing the device in the all banks

idle state.

8.Issue an AUTO REFRESH command.

9.Wait at least t RFC time, during which only NOPs or COMMAND INHIBIT commands

are allowed.

10.Issue an AUTO REFRESH command.

11.Wait at least t RFC time, during which only NOPs or COMMAND INHIBIT commands

are allowed.

12.The SDRAM is now ready for mode register programming. Because the mode register

will power up in an unknown state, it should be loaded with desired bit values prior to

applying any operational command. Using the LMR command, program the mode

register. The mode register is programmed via the MODE REGISTER SET command

with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again

or the device loses power. Not programming the mode register upon initialization will

result in default settings which may not be desired. Outputs are guaranteed High-Z

after the LMR command is issued. Outputs should be High-Z already before the LMR

command is issued.

13.Wait at least t MRD time, during which only NOP or DESELECT commands are

allowed.

At this point the DRAM is ready for any valid command.

Note:If desired, more than two AUTO REFRESH commands can be issued in the sequence.

After steps 9 and 10 are complete, repeat them until the desired number of AUTO

REFRESH + t RFC loops is achieved.

Register Definition

Mode Register

The mode register is used to define the specific mode of operation of the SDRAM. This

definition includes the selection of a burst length (BL), a burst type, a CAS latency (CL),

an operating mode and a write burst mode, as shown in Figure4 on page12. The mode

register is programmed via the LOAD MODE REGISTER command and will retain the

stored information until it is programmed again or the device loses power.

Mode register bits M0–M2 specify the, M3 specifies the type of burst (sequential or inter-

leaved), M4–M6 specify the CL, M7 and M8 specify the operating mode, M9 specifies the

write burst mode, and M10, M11, BA0, and BA1 are reserved for future use.

The mode register must be loaded when all banks are idle, and the controller must wait

the specified time before initiating the subsequent operation. Violating either of these

requirements will result in unspecified operation.

Burst Length (BL)

Read and write accesses to the SDRAM are burst oriented, with BL being programmable,

as shown in Figure4 on page12. The BL determines the maximum number of column

locations that can be accessed for a given READ or WRITE command. Burst lengths of 1,

2, 4, or 8 locations are available for both the sequential and the interleaved burst types,

and a full-page burst is available for the sequential type. The full-page burst is used in

conjunction with the BURST TERMINATE command to generate arbitrary BLs.Reserved states should not be used, as unknown operation or incompatibility with

future versions may result.

When a READ or WRITE command is issued, a block of columns equal to BL is effectively

selected. All accesses for that burst take place within this block, meaning that the burst

will wrap within the block if a boundary is reached. The block is uniquely selected by A1–

A7 when BL = 2; by A2–A7 when BL = 4; and by A3–A7 when BL = 8. The remaining (least

significant) address bit(s) is (are) used to select the starting location within the block.

Full-page bursts wrap within the page if the boundary is reached.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved;

this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by BL, the burst type and the

starting column address, as shown in Table6 on page13.

Figure 4: Mode Register Definition

Notes:

1.For a BL = 2, A1–A7 select the block-of-two burst; A0 selects the starting column within the block.

2.For a BL = 4, A2–A7 select the block-of-four burst; A0–A1 select the starting column within

the block.

3.For a BL = 8, A3–A7 select the block-of-eight burst; A0–A2 select the starting column within the block.

4.For a full-page burst, the full row is selected and A0–A7 select the starting column.

5.Whenever a boundary of the block is reached within a given sequence above, the following

access wraps within the block.

6.For a BL = 1, A0–A7 select the unique column to be accessed, and mode register bit M3 is ignored.

Table 6: Burst Definition

Burst

Length

Starting Column

Address Order of Accesses Within a Burst Type = Sequential

Type = Interleaved

2

A000-10-11

1-01-04

A1A0000-1-2-30-1-2-3011-2-3-01-0-3-2102-3-0-12-3-0-111

3-0-1-23-2-1-08

A2A1A00000-1-2-3-4-5-6-70-1-2-3-4-5-6-70011-2-3-4-5-6-7-01-0-3-2-5-4-7-60102-3-4-5-6-7-0-12-3-0-1-6-7-4-50113-4-5-6-7-0-1-23-2-1-0-7-6-5-41004-5-6-7-0-1-2-34-5-6-7-0-1-2-31015-6-7-0-1-2-3-45-4-7-6-1-0-3-21106-7-0-1-2-3-4-56-7-4-5-2-3-0-11117-0-1-2-3-4-5-67-6-5-4-3-2-1-0Full Page (256)

n = A0–A7 (Location

0–256)

Cn, Cn + 1, Cn + 2Cn + 3, Cn + 4... Cn - 1, Cn…

Not supported

The CL is the delay, in clock cycles, between the registration of a READ command and

the availability of the first piece of output data. The latency can be set to one, two or

three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data

will be available by clock edge n + m. The DQs will start driving as a result of the clock

edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,

the data will be valid by clock edge n + m. For example, assuming that the clock cycle

time is such that all relevant access times are met, if a read command is registered at T0

and the latency is programmed to two clocks, the DQs will start driving after T1 and the

data will be valid by T2, as shown in Figure5. Table7 below indicates the operating

frequencies at which each CL setting can be used.

Figure 5: CAS Latency

Reserved states should not be used as unknown operation or incompatibility with future

versions may result.Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other combi-

nations of values for M7 and M8 are reserved for future use and/or test modes. The

programmed BL applies to both read and write bursts.

Test modes and reserved states should not be used because unknown operation or

incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, BL programmed via M0–M2 applies to both read and write bursts; when

M9 = 1, the programmed BL applies to read bursts, but write accesses are single-location

(nonburst) accesses.

Table 7: CAS Latency

Speed

Allowable Operating Frequency (MHz)

CL = 1CL = 2CL = 3

-6≤ 50≤ 100≤ 166 -7≤ 50≤ 100≤ 143

Commands

Table 8 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following the Operation section; these tables provide current state/next state information.

Notes:

1.CKE is HIGH for all commands shown except SELF REFRESH.

2.A0–A11 define the op-code written to the mode register.

3.A0–A11 provide row address, BA0 and BA1 determine which bank is made active.

4.

A0–A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersis-tent), while A10 LOW disables the auto precharge feature; BA0 and BA1 determine which bank is being read from or written to.

5.A10 LOW: BA0 and BA1 determine the bank being precharged. A10 HIGH: All banks pre-charged and BA0 and BA1 are “Don’t Care.”

6.This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.

7.Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8.

Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0 controls DQ0–DQ7; DQM1 controls DQ8–DQ15; DQM2 controls DQ16–DQ23; and DQM3 controls DQ24–DQ31.

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-lected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

Table 8:

Truth Table–Commands and DQM Operation

(Note: 1)

NAME (FUNCTION)

CS#RAS#CAS#WE#DQM ADDR DQs NOTES

COMMAND INHIBIT (NOP) H X X X X X X NO OPERATION (NOP)

L H H H X X X ACTIVE (Select bank and activate row)

L L H H X Bank/Row X 3READ (Select bank and column, and start READ burst) L H L H L/H8Bank/Col X 4WRITE (Select bank and column, and start WRITE burst)L H L L L/H8Bank/Col

Valid 4BURST TERMINATE

L H H L X X Active PRECHARGE (Deactivate row in bank or banks)L L H L X Code X 5AUTO REFRESH or SELF REFRESH (Enter self refresh mode)L L L H X X X 6,

7LOAD MODE REGISTER

L L L L X Op-Code

X 2Write Enable/Output Enable ––––L –Active 8Write Inhibit/Output High-Z

–

–

–

–

H

–

High-Z

8

The mode register is loaded via inputs A0–A11. See the Mode Register heading in the

“Register Definition” section. The LOAD MODE REGISTER command can only be issued

when all banks are idle, and a subsequent executable command cannot be issued until

t MRD is met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a

subsequent access. The value on the BA0 and BA1 inputs selects the bank, and the

address provided on inputs A0–A11 selects the row. This row remains active (or open)

for accesses until a precharge command is issued to that bank. A precharge command

must be issued before opening a different row in the same bank.

READ

The READ command is used to initiate a burst read access to an active row. The value on

the BA0 and BA1 (B1) inputs selects the bank, and the address provided on inputs A0–A7

selects the starting column location. The value on input A10 determines whether or not

auto precharge is used. If auto precharge is selected, the row being accessed will be

precharged at the end of the read burst; if auto precharge is not selected, the row will

remain open for subsequent accesses. Read data appears on the DQs subject to the logic

level on the DQM inputs two clocks earlier. If a given DQMx signal was registered HIGH,

the corresponding DQs will be High-Z two clocks later; if the DQMx signal was registered

LOW, the corresponding DQs will provide valid data. DQM0 corresponds to DQ0–DQ7,

DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23 and DQM3

corresponds to DQ24–DQ31.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value

on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A0–A7

selects the starting column location. The value on input A10 determines whether or not

auto precharge is used. If auto precharge is selected, the row being accessed will be

precharged at the end of the write burst; if auto precharge is not selected, the row will

remain open for subsequent accesses. Input data appearing on the DQs is written to the

memory array subject to the DQM input logic level appearing coincident with the data.

If a given DQM signal is registered LOW, the corresponding data will be written to

memory; if the DQM signal is registered HIGH, the corresponding data inputs will be

ignored, and a write will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or

the open row in all banks. The bank(s) will be available for a subsequent row access a

specified time (t RP) after the precharge command is issued. Input A10 determines

whether one or all banks are to be precharged, and in the case where only one bank is to

be precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated

as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be

activated prior to any READ or WRITE commands being issued to that bank.

Auto Precharge

Auto precharge is a feature which performs the same individual-bank precharge func-

tion described above, without requiring an explicit command. This is accomplished by

using A10 to enable auto precharge in conjunction with a specific READ or WRITEcommand. A precharge of the bank/row that is addressed with the READ or WRITE

command is automatically performed upon completion of the READ or WRITE burst,

except in the full-page burst mode, where auto precharge does not apply. Auto

precharge is nonpersistent in that it is either enabled or disabled for each individual

Read or Write command.

auto precharge ensures that the precharge is initiated at the earliest valid stage within a

burst. The user must not issue another command to the same bank until the precharge

time (t RP) is completed. This is determined as if an explicit PRECHARGE command was

issued at the earliest possible time, as described for each burst type in the “Operation”

section of this data sheet.

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or full-page

bursts. The most recently registered READ or WRITE command prior to the BURST

TERMINATE command will be truncated, as shown in the “Operation” section.

The BURST TERMINATE command does not precharge the row; the row will remain

open until a PRECHARGE command is issued.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the SDRAM and is analogous to

CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonper-

sistent, so it must be issued each time a refresh is required.

The addressing is generated by the internal refresh controller. This makes the address

bits “Don’t Care” during an AUTO REFRESH command. The 128Mb SDRAM requires

4,096 AUTO REFRESH cycles every ms (t REF), regardless of width option. Providing a

distributed AUTO REFRESH command every 15.625µs will meet the refresh requirement

and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands

can be issued in a burst at the minimum cycle rate (t RFC), once every ms.

SELF REFRESH

The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest

of the system is powered down. When in the self refresh mode, the SDRAM retains data

without external clocking. The SELF REFRESH command is initiated like an AUTO

REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command

is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of

CKE, which must remain LOW.

Once self refresh mode is engaged, the SDRAM provides its own internal clocking,

causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh

mode for a minimum period equal to t RAS and may remain in self refresh mode for an

indefinite period beyond that.

The procedure for exiting self refresh requires a sequence of commands. First, CLK must

be stable (stable clock is defined as a signal cycling within timing constraints specified

for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must

have NOP commands issued (a minimum of two clocks) for t XSR because time is

required for the completion of any internal refresh in progress.

Upon exiting SELF REFRESH mode, AUTO REFRESH commands must be issued every

15.625µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh

counter.

Operation

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row

in that bank must be “opened.” This is accomplished via the ACTIVE command, which

selects both the bank and the row to be activated. See Figure6.

After opening a row (issuing an ACTIVE command), a READ or WRITE command may be

issued to that row, subject to the t RCD specification. t RCD (MIN) should be divided by

the clock period and rounded up to the next whole number to determine the earliest

clock edge after the ACTIVE command on which a READ or WRITE command can be

issued. For example, a t RCD specification of 20ns with a 125 MHz clock (8ns period)

results in 2.5 clocks, rounded to 3. This is reflected in Figure7, which covers any case

where 2 < t RCD (MIN)/t CK - 3. (The same procedure is used to convert other specifica-

tion limits from time units to clock cycles.)

A subsequent ACTIVE command to a different row in the same bank can only be issued

after the previous active row has been “closed” (precharged). The minimum time

interval between successive ACTIVE commands to the same bank is defined by t RC.

A subsequent ACTIVE command to another bank can be issued while the first bank is

being accessed, which results in a reduction of total row-access overhead. The

minimum time interval between successive ACTIVE commands to different banks is

defined by t RRD.

Figure 6: Activating a Specific Row in a Specific Bank

Figure 7: Example: Meeting t RCD (MIN) When 2 < t RCD (MIN)/t CK< 3

Notes: 1.t RCD (MIN) = 20ns, t CK = 8ns

t RCD (MIN) × t CK

where x = number of clocks for equation to be true.

READs

READ bursts are initiated with a READ command, as shown in Figure8.

The starting column and bank addresses are provided with the READ command, and

auto precharge is either enabled or disabled for that burst access. If auto precharge is

enabled, the row being accessed is precharged at the completion of the burst. For the

generic READ commands used in the following illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address will

be available following the CL after the READ command. Each subsequent data-out

element will be valid by the next positive clock edge. Figure9 shows general timing for

each possible CL setting.

Figure 8: READ Command

Upon completion of a burst, assuming no other commands have been initiated, the DQs

will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it

will wrap to column 0 and continue.)

Data from any READ burst may be truncated with a subsequent READ command, and

data from a fixed-length READ burst may be immediately followed by data from a READ

command. In either case, a continuous flow of data can be maintained. The first data

element from the new burst follows either the last element of a completed burst or the

last desired data element of a longer burst that is being truncated. The new READ

command should be issued x cycles before the clock edge at which the last desired data

element is valid, where x = CL - 1. This is shown in Figure10 on page22 for CAS latencies

of one, two and three; data element n + 3 is either the last of a burst of four or the last

desired of a longer burst. This 128Mb SDRAM uses a pipelined architecture and there-

fore does not require the 2n rule associated with a prefetch architecture.

Figure 9: CAS Latency

A READ command can be initiated on any clock cycle following a previous READ

command. Full-speed random read accesses can be performed to the same bank, as

shown in Figure11 on page23, or each subsequent READ may be performed to a

different bank.Figure 10: Consecutive READ Bursts

Notes: 1.Each READ command may be to either bank. DQM is LOW.Figure 11: Random READ Accesses

Notes: 1.Each READ command may be to either bank. DQM is LOW.

Data from any READ burst may be truncated with a subsequent WRITE command, and

data from a fixed-length READ burst may be immediately followed by data from a

WRITE command (subject to bus turnaround limitations). The WRITE burst may be

initiated on the clock edge immediately following the last (or last desired) data element

from the READ burst, provided that I/O contention can be avoided. In a given system

design, there may be a possibility that the device driving the input data will go Low-Z

before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur

between the last read data and the WRITE command.Figure 12: READ-to-WRITE

Notes: 1.CL = 3is used for illustration. The READ command may be to any bank, and the WRITE com-

mand may be to any bank. If a burst of one is used, then DQM is not required.

The DQM input is used to avoid I/O contention, as shown in Figures12 and 13. The

DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command

(DQM latency is two clocks for output buffers) to suppress data-out from the READ.

Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z),

regardless of the state of the DQM signal; provided the DQM was active on the clock just

prior to the WRITE command that truncated the READ command. If not, the second

WRITE will be an invalid WRITE. For example, if DQM was low during T4 in Figure13,

then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.

The DQM signal must be de-asserted prior to the WRITE command (DQM latency is

zero clocks for input buffers) to ensure that the written data is not masked. Figure12

shows the case where the clock frequency allows for bus contention to be avoided

without adding a NOP cycle, and Figure13 shows the case where the additional nop is

needed.

Figure 13: READ-to-WRITE with Extra Clock Cycle

Notes: 1.CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE com-

mand may be to any bank.

A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE

command to the same bank (provided that auto precharge was not activated), and a full-

page burst may be truncated with a PRECHARGE command to the same bank. The

PRECHARGE command should be issued x cycles before the clock edge at which the last

desired data element is valid, where x = CL - 1. This is shown in Figure14 for each

possible CL; data element n + 3 is either the last of a burst of four or the last desired of a

longer burst. Following the PRECHARGE command, a subsequent command to the

same bank cannot be issued until t RP is met. Note that part of the row precharge time is

hidden during the access of the last data element(s).

Figure 14: READ-to-PRECHARGE

Notes: 1.DQM is LOW.

In the case of a fixed-length burst being executed to completion, a PRECHARGE

command issued at the optimum time (as described above) provides the same opera-

tion that would result from the same fixed-length burst with auto precharge. The disad-

vantage of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command; the advantage of the

PRECHARGE command is that it can be used to truncate fixed-length or full-page

bursts.Full-page READ bursts can be truncated with the BURST TERMINATE command, and

fixed-length READ bursts may be truncated with a BURST TERMINATE command,

provided that auto precharge was not activated. The BURST TERMINATE command

should be issued x cycles before the clock edge at which the last desired data element is

valid, where x = CL - 1. This is shown in Figure15 for each possible CL; data element n +

3 is the last desired data element of a longer burst.

Figure 15: Terminating a READ Burst

Notes: 1.DQM is LOW.WRITEs

WRITE bursts are initiated with a WRITE command, as shown in Figure16.

The starting column and bank addresses are provided with the WRITE command, and

auto precharge is either enabled or disabled for that access. If auto precharge is enabled,

the row being accessed is precharged at the completion of the burst. For the generic

WRITE commands used in the following illustrations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element will be registered coincident with

the WRITE command. Subsequent data elements will be registered on each successive

positive clock edge. Upon completion of a fixed-length burst, assuming no other

commands have been initiated, the DQs will remain High-Z and any additional input

data will be ignored (see Figure17 on page28). A full-page burst will continue until

terminated. (At the end of the page, it will wrap to column 0 and continue.)

Figure 16: WRITE Command

Data for any WRITE burst may be truncated with a subsequent WRITE command, and

data for a fixed-length WRITE burst may be immediately followed by data for a WRITE

command. The new WRITE command can be issued on any clock following the previous

WRITE command, and the data provided coincident with the new command applies to

the new command. An example is shown in Figure18 on page28. Data n + 1 is either the

last of a burst of two or the last desired of a longer burst. This 128Mb SDRAM uses a

pipelined architecture and therefore does not require the 2n rule associated with a

prefetch architecture. A WRITE command can be initiated on any clock cycle following a

previous WRITE command. Full-speed random write accesses within a page can be

performed to the same bank, as shown in Figure19 on page28, or each subsequent

WRITE may be performed to a different bank.Figure 17: WRITE Burst

Notes: 1.BL = 2. DQM is LOW.

Figure 18: WRITE-to0WRITE

Notes: 1.DQM is LOW. Each WRITE command may be to any bank. Figure 19: Random WRITE Cycles

Notes: 1.Each WRITE command may be to any bank. DQM is LOW.Figure 20: WRITE-to-READ

Notes: 1.The WRITE command may be to any bank, and the READ command may be to any bank.

DQM is LOW. CL = 2 for illustration.

Data for any WRITE burst may be truncated with a subsequent READ command, and

data for a fixed-length WRITE burst may be immediately followed by a READ command.

Once the READ command is registered, the data inputs will be ignored, and writes will

not be executed. An example is shown in Figure20. Data n + 1 is either the last of a burst

of two or the last desired of a longer burst.

Data for a fixed-length WRITE burst may be followed by, or truncated with, a

PRECHARGE command to the same bank (provided that auto precharge was not acti-

vated), and a full-page WRITE burst may be truncated with a PRECHARGE command to

the same bank. The PRECHARGE command should be issued t W R after the clock edge at

which the last desired input data element is registered. The “two-clock” write-back

requires at least one clock plus time, regardless of frequency, in auto precharge mode. In

addition, when truncating a WRITE burst, the DQM signal must be used to mask input

data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE

command. An example is shown in Figure21. Data n + 1 is either the last of a burst of

two or the last desired of a longer burst. Following the PRECHARGE command, a subse-

quent command to the same bank cannot be issued until t RP is met. The precharge will

actually begin coincident with the clock-edge (T2 in Figure21 on page30) on a “one-

clock” t W R and sometime between the first and second clock on a “two-clock” t W R

(between T2 and T3 in Figure21.)

In the case of a fixed-length burst being executed to completion, a PRECHARGE

command issued at the optimum time (as described above) provides the same opera-

tion that would result from the same fixed-length burst with auto precharge. The disad-

vantage of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command; the advantage of the

PRECHARGE command is that it can be used to truncate fixed-length or full-page

bursts.Figure 21: WRITE-to-PRECHARGE

Notes: 1.DQM could remain LOW in this example if the WRITE burst is a fixed length of two.

Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE

command. When truncating a WRITE burst, the input data applied coincident with the

BURST TERMINATE command will be ignored. The last data written (provided that

DQM is LOW at that time) will be the input data applied one clock previous to the

BURST TERMINATE command. This is shown in Figure22, where data n is the last

desired data element of a longer burst.

Figure 22: Terminating a WRITE Burst

Notes: 1.DQMs are LOW.

Figure 23: PRECHARGE Command

PRECHARGE

The PRECHARGE command (Figure23) is used to deactivate the open row in a partic-

ular bank or the open row in all banks. The bank(s) will be available for a subsequent

row access some specified time (t RP) after the precharge command is issued. Input A10

determines whether one or all banks are to be precharged, and in the case where only

one bank is to be precharged, inputs BA0 and BA1 select the bank. When all banks are to

be precharged, inputs BA0 and BA1 are treated as “Don’t Care.” Once a bank has been

precharged, it is in the idle state and must be activated prior to any READ or WRITE

commands being issued to that bank.

Power-Down

Power-down occurs if CKE is registered low coincident with a NOP or COMMAND

INHIBIT when no accesses are in progress (see Figure24 on page32). If power-down

occurs when all banks are idle, this mode is referred to as precharge power-down; if

power-down occurs when there is a row active in either bank, this mode is referred to as

active power-down. Entering power-down deactivates the input and output buffers,

excluding CKE, for maximum power savings while in standby. The device may not

remain in the power-down state longer than the refresh period (ms) since no refresh

operations are performed in this mode.

The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE

HIGH at the desired clock edge (meeting t CKS).Figure 24: Power-Down

Clock Suspend

The clock suspend mode occurs when a column access/burst is in progress and CKE is

registered low. In the clock suspend mode, the internal clock is deactivated, “freezing”

the synchronous logic.

For each positive clock edge on which CKE is sampled LOW, the next internal positive

clock edge is suspended. Any command or data present on the input pins at the time of a

suspended internal clock edge is ignored; any data present on the DQ pins remains

driven; and burst counters are not incremented, as long as the clock is suspended. (See

examples in Figures22 and 23.)

Clock suspend mode is exited by registering CKE HIGH; the internal clock and related

operation will resume on the subsequent positive clock edge.

Figure 25: CLOCK SUSPEND During WRITE Burst

Notes: 1.For this example, BL = 4 or greater, and DM is LOW.Figure 26: CLOCK SUSPEND During READ Burst

Notes: 1.For this example, CL = 2, BL = 4 or greater, and DQM is LOW.

Burst READ/Single WRITE

The burst read/single write mode is entered by programming the write burst mode bit

(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the

access of a single column location (burst of one), regardless of the programmed BL.

READ commands access columns according to the programmed BL and sequence, just

as in the normal mode of operation (M9 = 0).

Concurrent Auto Precharge

An access command to (READ or WRITE) another bank while an access command with

auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM

supports concurrent auto precharge. Micron SDRAMs support concurrent auto

precharge. Four cases where concurrent auto precharge occurs are defined below.

READ with Auto Precharge

1.Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-

rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ

to bank m is registered (see Figure27 on page34).

2.Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will

interrupt a READ on bank n when registered. DQM should be used two clocks prior to

the WRITE command to prevent bus contention. The precharge to bank n will begin

when the WRITE to bank m is registered (see Figure28 on page34).Figure 27: READ With Auto Precharge Interrupted by a READ

Notes: 1.DQM is LOW.

Figure 28: READ With Auto Precharge Interrupted by a WRITE

Notes: 1.DQM is HIGH at T2 to prevent D OUT a + 1 from contending with D IN d at T4.

WRITE with Auto Precharge

2.Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-

rupt a WRITE on bank n when registered, with the data-out appearing CL later. The

precharge to bank n will begin after t W R is met, where t W R begins when the READ to

bank m is registered. The last valid WRITE to bank n will be data-in registered one

clock prior to the READ to bank m (see Figure29 on page35).

3.Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will

interrupt a WRITE on bank n when registered. The precharge to bank n will begin

after t W R is met, where t W R begins when the WRITE to bank m is registered. The last

valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank

m (see Figure30 on page35).Figure 29: WRITE With Auto Precharge Interrupted by a READ

Notes: 1.DQM is LOW.

Figure 30: WRITE With Auto Precharge Interrupted by a WRITE

Notes: 1.DQM is LOW.Table 9: Truth Table – CKE

(Notes: 1–4)

CKE n-1CKE n Current State COMMAND n ACTION n Notes L L Power-Down X Maintain power-Down

Self refresh X Maintain self refresh

Clock Suspend X Maintain clock suspend L H Power-Down COMMAND INHIBIT or NOP Exit power-down5

Self refresh COMMAND INHIBIT or NOP Exit self refresh6

Clock suspend X Exit clock suspend7

H L All banks idle COMMAND INHIBIT or NOP Power-Down entry

All banks idle AUTO REFRESH self refresh Entry

Reading or writing VALID Clock suspend entry

H H See Table10 on page37

Notes: 1.CKE n is the logic state of CKE at clock edge n; CKE n-1 was the state of CKE at the previous

clock edge.

2.Current state is the state of the SDRAM immediately prior to clock edge n.

3.COMMAND n is the command registered at clock edge n, and ACTION n is a result of COM-

MAND n.

4.All states and sequences not shown are illegal or reserved.

5.Exiting power-down at clock edge n will put the device in the all banks idle state in time for

clock edge n + 1 (provided that t CKS is met).

6.Exiting self refresh at clock edge n will put the device in the all banks idle state once t XSR is

met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring

during the t XSR period. A minimum of two NOP commands must be provided during t XSR

period.

7.After exiting clock suspend at clock edge n, the device will resume operation and recognize

the next command at clock edge n + 1.

Notes:

1.This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 9 on page 36) and after t XSR has been met (if the previous state was self refresh).

2.This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3.Current state definitions:

4.The following states must not be interrupted by a command issued to the same bank. COM-MAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Table 10 on page 37, and according to Table 11 on page 39.

Table 10:

Truth Table – Current State Bank n , Command To Bank n

Notes: 1–6; notes appear below table

Current State CS#RAS#CAS#WE#COMMAND (ACTION)

Notes

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)L H H H NO OPERATION (NOP/Continue previous operation)Idle

L L H H ACTIVE (Select and activate row)L L L H AUTO REFRESH

7L L L L LOAD MODE REGISTER 7L L H L PRECHARGE

11Row

active

L H L H READ (Select column and start READ burst)10L H L L WRITE (Select column and start WRITE burst) 10L L H L PRECHARGE (Deactivate row in bank or banks)8Read (auto precharge disabled)L H L H READ (Select column and start new READ burst)10L H L L WRITE (Select column and start WRITE burst)

10L L H L PRECHARGE (Truncate READ burst, start precharge)8L H H L BURST TERMINATE

Write (auto precharge disabled)L H L H READ (Select column and start READ burst)

10L H L L WRITE (Select column and start new WRITE burst) 10L L H L PRECHARGE (Truncate WRITE burst, start precharge)8L H

H

L

BURST TERMINATE

9

Idle:The bank has been precharged, and t RP has been met.

Row active:A row in the bank has been activated, and t RCD has been met. No data

bursts/accesses and no register accesses are in progress.

Read:A READ burst has been initiated, with auto precharge disabled, and has not

yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not

yet terminated or been terminated.Precharging:Starts with registration of a PRECHARGE command and ends when

t RP is met. Once t RP is met, the bank will be in the idle state.

Row activating:Starts with registration of an ACTIVE command and ends when t RCD

is met. Once t RCD is met, the bank will be in the row active state.

Read w/auto precharge enabled:Starts with registration of a READ command with auto precharge

enabled and ends when t RP has been met. Once t RP is met, the bank

will be in the idle state.

Write w/auto precharge enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when t RP has been met. Once t RP is met, the bank

will be in the idle state.

5.The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states.

6.All states and sequences not shown are illegal or reserved.

7.Not bank-specific; requires that all banks are idle.

8.May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.

9.Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-less of bank.

10.READs or WRITEs listed in the Command (Action) column include READs or WRITEs with

auto precharge enabled and READs or WRITEs with auto precharge disabled.11.Does not affect the state of the bank and acts as a NOP to that bank.

Refreshing:Starts with registration of an AUTO REFRESH command and ends

when t RFC is met. Once t RFC is met, the SDRAM will be in the all banks idle state.

Accessing mode register:Starts with registration of a LOAD MODE REGISTER command and

ends when t MRD has been met. Once t MRD is met, the SDRAM will

be in the all banks idle state.

Precharging all:Starts with registration of a PRECHARGE ALL command and ends

when t RP is met. Once t RP is met, all banks will be in the idle state.

Notes:

1.This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 9 on page 36) and after t XSR has been met (if the previous state was self refresh).

2.This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.

3.Current state definitions:

4.AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.

Table 11:

Truth Table – CURRENT STATE BANK n , COMMAND TO BANK m

Notes: 1–6; notes appear below and on next page

Current State

CS#RAS#CAS#WE#COMMAND (ACTION)

Notes

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)L H H H NO OPERATION (NOP/Continue previous operation)Idle

X X X X Any Command Otherwise Allowed to Bank m Row activating, active, or precharging L L H H ACTIVE (Select and activate row)

L H L H READ (Select column and start READ burst)7L H L L WRITE (Select column and start WRITE burst) 7

L L H L PRECHARGE

Read (auto precharge disabled)L L H H ACTIVE (Select and activate row)

L H L H READ (Select column and start new READ burst)7, 10L H L L WRITE (Select column and start WRITE burst) 7, 11L L H L PRECHARGE

9Write (auto precharge disabled)L L H H ACTIVE (Select and activate row)

L H L H READ (Select column and start READ burst)

7, 12L H L L WRITE (Select column and start new WRITE burst) 7, 13L L H L PRECHARGE

9Read (with auto precharge)

L L H H ACTIVE (Select and activate row)

L H L H READ (Select column and start new READ burst)7, 8, 14L H L L WRITE (Select column and start WRITE burst) 7, 8, 15L L H L PRECHARGE

9Write (with auto precharge)

L L H H ACTIVE (Select and activate row)

L H L H READ (Select column and start READ burst)

7, 8, 16L H L L WRITE (Select column and start new WRITE burst) 7, 8, 17L L

H

L

PRECHARGE

9

Idle:The bank has been precharged, and t RP has been met.

Row Active:A row in the bank has been activated, and t RCD has been met. No

data bursts/accesses and no register accesses are in progress.

Read:A READ burst has been initiated, with auto precharge disabled, and

has not yet terminated or been terminated.

Write:A WRITE burst has been initiated, with auto precharge disabled, and

has not yet terminated or been terminated.

Read w/Auto Precharge Enabled:Starts with registration of a READ command with auto precharge enabled, and ends when t RP has been met. Once t RP is met, the

bank will be in the idle state.

Write w/Auto Precharge Enabled:Starts with registration of a WRITE command with auto precharge enabled, and ends when t RP has been met. Once t RP is met, the

bank will be in the idle state.

7.READs or WRITEs to bank m listed in the Command (Action) column include READs or

WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.

8.Concurrent auto precharge: Bank n will initiate the auto precharge command when its

burst has been interrupted by bank m’s burst.

9.Burst in bank n continues as initiated.

10.For a READ without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the READ on bank n, CL later (see Figure10). 11.For a READ without auto precharge interrupted by a WRITE (with or without auto pre-

charge), the WRITE to bank m will interrupt the READ on bank n when registered (see Figure12 and Figure13). DQM should be used one clock prior to the WRITE command to prevent bus contention.

12.For a WRITE without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the WRITE on bank n when registered (see Figure20), with the data-out appearing CL later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.

13.For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-

charge), the WRITE to bank will interrupt the WRITE on bank n when registered (see

Figure18). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.

14.For a READ with auto precharge interrupted by a READ (with or without auto precharge),

the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n will begin when the READ to bank m is registered (see Figure27).

15.For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),

the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (see Figure28).

16.For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),

the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CL later. The PRECHARGE to bank n will begin after t WR is met, where t WR begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in registered one clock prior to the READ to bank m (see Figure29).

17.For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),

the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after t WR is met, where t WR begins when the WRITE to bank m is reg-istered. The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m (see Figure30).Electrical Specifications

Stresses greater than those listed Table12 may cause permanent damage to the device.

This is a stress rating only, and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

Table 12: Absolute Maximum Ratings

Parameter Min Max Units Voltage on V DD, V DD Q supply relative to V SS–1+4.6V Voltage on inputs, NC or I/O pins relative to V SS–1+4.6V Operating temperature, T A0+70°C Storage temperature (plastic)–55+150°C Power dissipation1W Operating temperature, T A (IT)–40+85°C

Temperature and Thermal Impedance

It is imperative that the SDRAM device’s temperature specifications, shown in Table13

on page42, be maintained in order to ensure the junction temperature is in the proper

operating range to meet data sheet specifications. An important step in maintaining the

proper junction temperature is using the device’s thermal impedances correctly. The

thermal impedances are listed in Table14 on page42 for the applicable die revision and

packages being made available. These thermal impedance values vary according to the

density, package, and particular design used for each device.

Incorrectly using thermal impedances can produce significant errors. Read Micron

technical note TN-00-08, “Thermal Applications” prior to using the thermal impedances

listed in Table14. To ensure the compatibility of current and future designs, contact

Micron Applications Engineering to confirm thermal impedance values.

The SDRAM device’s safe junction temperature range can be maintained when the T C

specification is not exceeded. In applications where the device's ambient temperature is

too high, use of forced air and/or heat sinks may be required in order to satisfy the case

temperature specifications.

Notes:

1.MAX operating case temperature, T C , is measured in the center of the package on the top side of the device, as shown in Figure 31 and Figure 32 on page 43.

2.Device functionality is not guaranteed if the device exceeds maximum T C during operation.

3.Both temperature specifications must be satisfied

4.The case temperature should be measured by gluing a thermocouple to the top center of the component. This should be done with a 1mm bead of conductive epoxy, as defined by the JEDEC EIA/JESD51 standards. Care should be taken to ensure the thermocouple bead is touching the case.

5.Operating ambient temperature surrounding the package.

Notes:

1.For designs expected to last beyond the die revision listed, contact Micron Applications Engineering to confirm thermal impedance values.

2.Thermal resistance data is sampled from multiple lots and the values should be viewed as

typical.

3.These are estimates; actual results may vary.

Table 13:

Temperature Limits

Parameter

Symbol Min Max Units Notes Operating case temperature:Commercial Industrial

T C

0-408090

°C

1, 2, 3, 4

Junction temperature:Commercial Industrial

T J

0-408595

°C

3

Ambient temperature:Commercial Industrial

T A

0-407085°C

3, 5Peak reflow temperature

T PEAK

–

260

°C

Table 14: Thermal Impedance Simulated Values

Die Revision Package Substrate θ JA (°C/W) Airflow = 0m/s

θ JA (°C/W) Airflow = 1m/s

θ JA (°C/W) Airflow = 2m/s

θ JB (°C/W)

θ JC (°C/W)

G

86-pin TSOP 2-layer 82.26559.749.410.34-layer 5547.245.140.690-ball VFBGA 2-layer .650.845.337.5 1.8

4-layer

48.2

41.1

38.1

32.1

Figure 31: Example Temperature Test Point Location, 54-Pin TSOP: Top View

Figure 32: Example Temperature Test Point Location, 90-Ball VFBGA: Top View

Table 15: DC Electrical Characteristics and Operating Conditions

Notes: 1, 6; notes appear on page47; V DD = +3.3V ±0.3V, V DD Q = +3.3V ±0.3V

Parameter/Condition Symbol Min Max Units Notes Supply voltage V DD, V DD Q3 3.6V

Input high voltage: Logic 1; All inputs V IH2V DD + 0.3V22 Input low voltage: Logic 0; All inputs Vil–0.30.8V22 Input leakage current:

Any input 0V ≤ V IN≤ V DD (All other pins not under test = 0V)

I I–55µA

Output leakage current:

DQs are disabled; 0V ≤ V OUT≤ V DD Q

I OZ–55µA

Output levels:

)Output high voltage (I OUT = –4mA) Output low voltage (I OUT = 4mA)V OH 2.4–V V OL–0.4V

Table 16: I DD Specifications and Conditions

(Notes: 1, 6, 11, 13; notes appear on page47) (V DD, V DD Q = +3.3V ±0.3V)

Parameter/Condition Symbol

Max

Units Notes -6-7

Operating current: Active mode;

Burst = 2; READ or WRITE; t RC = t RC (MIN); CL = 3I DD1190165mA3, 18, 19,

26

Standby current: Power-Down mode;

CKE = LOW; All banks idle

I DD222mA

Standby current: Active mode; CS# = HIGH;

CKE = HIGH; All banks active after t RCD met;

No accesses in progress

I DD36555mA19, 26

Operating current: Burst mode; Continuous burst; READ or WRITE; All banks active, CL = 3I DD4195175mA3, 18, 19,

26

Auto refresh current: CL = 3; CKE, CS# = HIGH t RFC = t RFC (MIN)I DD5320320mA3, 12, 18,

19, 26

Self refresh current: CKE ≤ 0.2V I DD622mA4 Table 17: Capacitance

(Note: 2)

Parameter Symbol Min Max Units Input Capacitance: CLK C I1 2.5 4.0pF Input Capacitance: All other input-only pins C I2 2.5 4.0pF Input/Output Capacitance: DQs C I o 4.0 6.5pFTable 18: Electrical Characteristics and Recommended AC Operating Conditions Notes: 5, 6, 7, 8, 9, 11; notes appear on page47

AC Characteristics

Parameter Symbol

-6-7

Units Notes Min Max Min Max

Access time from CLK (pos. edge)CL = 3t AC (3) 5.5 5.5ns

CL = 2t AC (2)7.58ns

CL = 1t AC (1)1717ns Address hold time t AH11ns Address setup time t AS 1.52ns

CLK high-level width t CH 2.5 2.75ns

CLK low-level width t CL 2.5 2.75ns

Clock cycle time CL = 3 t CK (3)67ns23

CL = 2t CK (2)1010ns23

CL = 1t CK (1)2020ns23 CKE hold time t CKH11ns

CKE setup time t CKS 1.52ns

CS#, RAS#, CAS#, WE#, DQM hold time t CMH11ns

CS#, RAS#, CAS#, WE#, DQM setup time t CMS 1.52ns

Data-in hold time t DH11ns

Data-in setup time t DS 1.52ns

Data-out High-Z time CL = 3 t HZ (3) 5.5 5.5ns10

CL = 2 t HZ (2)7.58ns10

CL = 1t HZ (1)1717ns10 Data-out Low-Z time t LZ11ns

Data-out hold time t OH2 2.5 ns

ACTIVE to PRECHARGE command t RAS42120K42120K ns

ACTIVE to ACTIVE command period t RC6070ns

AUTO REFRESH period t RFC6070ns

ACTIVE to READ or WRITE delay t RCD1820ns

Refresh period (4,096 rows)t REFms PRECHARGE command period t RP1820ns

ACTIVE bank a to ACTIVE bank b command t RRD1214ns25 Transition time t T0.3 1.20.3 1.2 ns 7

Write recovery time t WR 1 CLK+

6ns 1 CLK+

7ns

t CK24

12ns14ns ns27 Exit self refresh to ACTIVE command t XSR7070ns20Table 19: AC Functional Characteristics

Notes: 5, 6, 7, 8, 9, 11; notes appear on page47

PARAMETER SYMBOL-6-7UNITS NOTES READ/WRITE command to READ/WRITE command t CCD11t CK

CKE to clock disable or power-down entry mode t CKED11t CK

CKE to clock enable or power-down exit setup mode t PED11t CK

DQM to input data delay t DQD00t CK

DQM to data mask during WRITEs t DQM00t CK

DQM to data High-Z during READs t DQZ22t CK

WRITE command to input data delay t DWD00t CK

Data-in to ACTIVE command CL = 3t DAL (3)55t CK

CL = 2t DAL (2)44t CK

CL = 1t DAL (1)33t CK

Data-in to PRECHARGE command t DPL22t CK

Last data-in to burst STOP command t BDL11t CK

Last data-in to new READ/WRITE command t CDL11t CK

Last data-in to PRECHARGE command t RDL22t CK

LOAD MODE REGISTER command to ACTIVE or REFRESH command t MRD22t CK

Data-out to High-Z from PRECHARGE command CL = 3t ROH (3)33t CK

CL = 2t ROH (2)22t CK

CL = 1t ROH (1)11t CKNotes

1.All voltages referenced to V SS.

2.This parameter is sampled. V DD, V DD Q = +

3.3V; f = 1 MHz, T A = 25°C; pin under test

biased at 1.4V. AC can range from 0pF to 6pF.

3.I DD is dependent on output loading and cycle rates. Specified values are obtained

with minimum cycle time and the outputs open.

4.Enables on-chip refresh and address counters.

5.The minimum specifications are used only to indicate cycle time at which proper

operation over the full temperature range (0°C ≤ T A≤ +70°C and –40°C ≤ T A≤ +85°C for

IT parts) is ensured.

6.An initial pause of 100µs is required after power-up, followed by two AUTO Refresh

commands, before proper device operation is ensured. (V DD and V DD Q must be pow-

ered up simultaneously. V SS and V SS Q must be at same potential.) The two AUTO

Refresh command wake-ups should be repeated any time the t REF refresh require-

ment is exceeded.

7.AC characteristics assume t T = 1ns.

8.In addition to meeting the transition rate specification, the clock and CKE must tran-

sit between V IH and V IL (or between V IL and V IH) in a monotonic manner.

9.Outputs measured at 1.5V with equivalent load:

10.t HZ defines the time at which the output achieves the open circuit condition; it is not

a reference to V OH or V OL. The last valid data element will meet t OH before going

High-Z.

11.AC timing and I DD tests have V IL = 0.25 and V IH = 2.75, with timing referenced to 1.5V

crossover point.

12.Other input signals are allowed to transition no more than once in any two-clock

period and are otherwise at valid V IH or V IL levels.

13.I DD specifications are tested after the device is properly initialized.

14.Timing actually specified by t CKS; clock(s) specified as a reference only at minimum

cycle rate.

15.Timing actually specified by t W R plus t RP; clock(s) specified as a reference only at

minimum cycle rate.

16.Timing actually specified by t W R.

17.Required clocks are specified by JEDEC functionality and are not dependent on any

timing parameter.

18.The I DD current will decrease as CL is reduced. This is due to the fact that the maxi-

mum cycle rate is slower as CL is reduced.

19.Address transitions average one transition every two clocks.

20.CLK must be toggled a minimum of two times during this period.

21.Based on t CK = 143 MHz for -7, 166 MHz for -6.

22.V IH overshoot: V IH (MAX) = V DD Q + 1.2V for a pulse width ≤ 3ns, and the pulse width

cannot be greater than one third of the cycle rate. V IL undershoot: V IL (MIN) = –1.2V

for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the

cycle rate.

23.The clock frequency must remain constant during access or precharge states (READ,

WRITE, including t W R, and PRECHARGE commands). CKE may be used to reduce the

data rate.24.Auto precharge mode only.

25.JEDEC and PC100 specify three clocks.

26.t CK = 7ns for -7, 6ns for -6.

27.Check factory for availability of specially screened devices having t W R = 10ns. t W R = 1

t CK for 100 MHz and slower (t CK = 10ns and higher) in manual precharge.

Timing Diagrams

Figure 33: Initialize and Load Mode Register

Notes: 1.The mode register may be loaded prior to the AUTO REFRESH cycles if desired.

2.Outputs are guaranteed High-Z after command is issued.Figure 34: Power-Down Mode

Notes: 1.Violating refresh requirements during power-down may result in a loss of data.下载本文