FLIP-FLOP(DETFF)

Troy A.Johnson§and Ivan S.Kourtev¶

§Department of Electrical Engineering¶Department of Electrical Engineering

Purdue University University of Pittsburgh Box213,1285Electrical Engineering Building348Benedum Hall

West Lafayette,Indiana47907-1285Pittsburgh,Pennsylvania15261 tajohnson@ieee.org ivan@ee.pitt.edu

Abstract—This paper describes an original circuit design of a static CMOS double-edge triggeredflip-flop(DETFF).Double-edge triggered(DET)flip-flops are bistableflip-flop circuits in which data is latched at either edge of the clock signal.Using suchflip-flops permits the rate of data processing to be preserved while using lower clock frequency(as compared to a circuit with single-edge triggeredflip-flops).Therefore,power consumption in DETFF based circuits may be reduced.The proposedflip-flop design has fewer transistors than other published static CMOS DETFFs.The described circuit structure is laid out in a05µm process.Circuit simulations using hspice demonstrate that the flip-flop is logically correct and functions as expected.Further-more,the proposed design rates favorably when compared to ex-isting static CMOS DETFF circuits.

I.I NTRODUCTION

In addition to size and speed trade-offs VLSI inte-grated circuit designers must give power strong con-sideration.For instance,wireless communications de-vices,hand-held and palm-top computers,and portable versions of microprocessors all require low power de-sign[1].Research has demonstrated that a significant portion of the power dissipated in an integrated cir-cuit is concentrated in the clock distribution network. Power dissipated in the clock distribution network may account for up to40-45%of the total integrated sys-tem power[2].By using double-edge triggeredflip-flops(DETFFs),the clock frequency can be significantly reduced—ideally,cut in half—while preserving the rate of data processing.Using lower clock frequency may translate into considerable power savings for the clocked portions of a circuit,including the clock distribution net-work andflip-flops.

Both double-edge triggered(DET)and single-edge triggered(SET)flip-flops are edge-sensitive devices,that is,data storage in theseflip-flops occurs at specific edges of the clock signal.During each clock period,single-edge triggeredflip-flops are triggered by and store data at only one—either the rising or the falling—edge of the clock signal.Double-edge triggeredflip-flops sample the input data at both the rising and the falling edges of the clock signal during each period of the clock signal. The proposed double-edge triggeredflip-flop circuit design is presented in Section II.This design is then compared to existing implementations of double-edge triggeredflip-flops in Section III.Concluding remarks are offered in Section IV.

II.C IRCUIT D ESIGN

A classical double-edge triggeredflip-flop in CMOS technology can be implemented as shown in Figure1.In this design,two opposite polarity level-sensitive latches

Fig.1.Classical DETFF implementation.

are used.Specifically,D1and D2are a positive level-sensitive and a negative level-sensitive latches,respec-tively,and,the block labeled M1is a multiplexer de-scribed by the equation y d0(a)Doubling the frequency of the clock signal.

G1

Y

X

D1

D

Q

Q

(b)Circuit structure of the DETFF.

Fig.2.Principle of operation of the proposed double-edge triggeredflip-flop.

CLK Y

CLK X CLK Z

Fig.3.Circuit schematic of the proposed single latch double-edge triggeredflip-flop.

circuit consider the circuit structure shown in Figure2(b)

and consisting of an exclusive or(XOR)gate G1and

a single negative level-sensitive latch D1.The purpose

of the XOR gate G1is to generate a special asymmetric

clock signal to drive the latch D1This clock signal has double the frequency of the system-wide clock signal,

thereby ensuring that a new data value is stored into the

latch at each edge of the system-wide clock signal.

The generation of this faster clock signal described in the previous paragraph is accomplished as illustrated in Figure2(a).The original system-wide clock signal CLK—labeled X in Figure2(a)—is inverted and delayed by a certain amount of time to produce the signal labeled Y Performing the XOR operation on the signals X and Y yields the desired clock signal whose frequency is dou-ble the frequency of the original system-wide clock sig-nal X.Observe that the duty cycle of the clock signal X Y is much less than50%since this signal is low for a very short period of time.Therefore,the negative level-sensitive latch shown in Figure2(b)is transparent for a very short amount of time,making it appear as if it were an edge-sensitiveflip-flop.

A complete circuit schematic of the proposed double-

edge triggeredflip-flop is shown in Figure3.The clock

driver is located on the top of Figure3and consists of four inverters.Note that excluding the transistors in the clock driver the proposed design consists of only ten(10) MOS transistors.The basic operation of theflip-flop is as previously described where the negative polarity level-sensitive latch appears in the lower right corner of Figure3and consists of the transistors Q5and Q6and the inverters G5and G6.

The clock driver—the circuit at the top of Figure3—is essentially a delay line for the clock signal CLK X, consisting of the inverters G1G2G3and G4.If each inverter G1through G4is assumed to introduce a delay τi,then the signals Y CLK and Z CLK are delayed from the clock signal X by3τi and4τi respectively.The clock driver is used to provide these delayed clock sig-nals to the exclusive-or(XOR)gate consisting of the transistors Q1through Q4in Figure3.

This XOR gate[3,4]computes the result of the oper-ation X Y CLK CLK.Had the signals X Y and Z not been delayed at all,the output of the XOR gate would have been a constant logic one(1).Because of the 3τi delay between the signals X and Y,however,there is a short period of time after each clock signal transition where X Y(Y has not changed yet).During this short period of time the XOR gate outputs a logic zero thereby turning on Q5and cutting off Q6.The latch at the right

Fig.4.Physical layout of the proposed single latch double-edge triggeredflip-flop.

in Figure3will be temporarily transparent and the input D will have a direct path to the output Q.

After a3τi delay the clock signal change has propa-

gated through the clock driver,the signals X and Y are

complementary(X Y)and the output of the XOR gate is logic high(1)again.The transistor Q5is cut off.The

data signal D has now been stored into the latch—Q6is conducting,thereby sustaining the latch feedback loop. Due to the direction of current in the feedback loop,the output signal Q is taken above the NMOS device and not below it to ensure a better voltage level when the output is high.If taken below the NMOS device,the output Q would suffer the threshold voltage drop for high outputs. An important consideration in this design is the num-ber of inverters in the clock driver.The3τi delay be-tween the clock signal X and the inverted clock signal Y must be sufficient to permit the XOR gate to fully eval-uate,to turn on the PMOS device Q5,and to allow the input D to charge/discharge the input to thefirst inverter. The amount of time necessary for these events to com-plete will differ depending on the technology and tran-sistor sizes used.With minimum transistor sizing and the AMI05µm(3-metal single poly)process,it was de-termined that the following condition must be satisfied: 345ps3τi575ps.The physical layout of theflip-flop is shown in Figure4.

III.C OMPARATIVE A NALYSIS

Several static DETflip-flops were selected from dif-

ferent sources,implemented in the same technology as

the proposedflip-flop,and tested in hspice with a

10MHz clock signal with100ps rise and fall times.Re-sults are shown in Table I.A relative ranking is provided

for each parameter measured for each design(the rank-

ing is a number in parentheses for each table entry with

1being the best).The maximum data frequency of the new DETflip-flop is estimated at up to1GHz.The proposed design is not the fastest device of the six but it

is considerably smaller than the two faster devices.Fur-

thermore,the power consumption(taken as the average

power from the beginning of a transition until4ns after-wards for each of the four possible output transitions)is the second lowest(almost43%of the third lowest).All aspects considered equal,the new design is an excellent overall choice and samples data at gigahertz speeds.

IV.C ONCLUDING R EMARKS

A fast,comparatively low power double-edge trig-

geredflip-flop can significantly improve the power con-

sumption of an electronic device by permitting the useTABLE I

S IMULATION R ESULTS(R ANKING)OF V ARIOUS T YPE OF S TATIC DETFF S.

2[5]4[6]6(new) Transistors8(1)18(5)10(2)

µm2363(3)588(6)374(4)

ps8105602250

D2D CQ C Q5502000820

ps580420400

D4D CQ C Q29024001220

ps650(2)598(1)1535(6)

D max D min19301670720 P1C Q63338136

µW7543061141

P3C Q88349125

µW799321710

P av P1P2P3P4479(1)346(4)141(2) Maximum Clock Frequency450417820

MHz2470(2)2666(1)658(6)

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