数字设计原理与实践

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题目：自动洗衣机控制器

姓名：魏玉峰

学号：2012171010009

1、任务与要求

设计内容：1）进行需求分析，确定总体框架；

          2）画出逻辑电路图；

          3）对设计电路进行仿真；

设计要求：假设自动洗衣机的定时操作顺序是，洗衣10min，排水2min，脱水3min，然后停止。设计出这个自动洗衣机的控制器。

设计提示：本设计有4个状态，分别为初始状、洗衣系统、排水系统、和脱水状态。当有复位信号时，系统进入循环控制状态，依次执行操作，可从信号灯观察到所处状态。

2、设计思路的介绍

    分析：洗衣机开机后，自动进入循环状态，分别进行洗衣10min，排水2min，脱水3min的操作，然后回到待机状态。任意期间输入复位信号都会重新开始进入循环控制状态。LED指示灯与当前操作对应，处于发光状态。

    由以上要求可知，所有状态共4种，分别为初始状态、洗衣状态、排水状态、和脱水状态，即用1个74163计时器，输出的状态与上面一一对应，具体见下表：

三、总体方案的选择

    经过多次选择与比较最终选择74163,7400来完成电路实现计时功能。将时钟信号设为1/60hz，即每分钟一个上升沿。电路中采用16个4输入与非门，1个12输入与非门，1个2输入与非门，1个3输入与非门。把每一个4输入与非门的四个角分别于74163的Qd、Qc、Qb、Qa相连，而每一个4输入与非门分别对应一个74163的输出状态。当所输出状态对应了洗衣机状态时，总输出状态将产生变化，从而进行当前操作，具体电路图设计如下：

Clk为时钟信号1/60hz

Input为开关按钮

Clr为复位按钮

Standby代表当前为待机状态

Washing代表当前为洗衣状态

Drainage代表当前为排水状态

Dehydration代表当前为洗衣状态

四、Verilog HDL 代码

module try3(

    clk,

    input,

    clr,

    Standby,

    Washing,

    Drainage,

    Dehydration

);

input    clk;

input    input;

input    clr;

output    Standby;

output    Washing;

output    Drainage;

output    Dehydration;

wire    SYNTHESIZED_WIRE_114;

wire    SYNTHESIZED_WIRE_115;

wire    SYNTHESIZED_WIRE_2;

wire    SYNTHESIZED_WIRE_116;

wire    SYNTHESIZED_WIRE_117;

wire    SYNTHESIZED_WIRE_5;

wire    SYNTHESIZED_WIRE_6;

wire    SYNTHESIZED_WIRE_7;

wire    SYNTHESIZED_WIRE_8;

wire    SYNTHESIZED_WIRE_9;

wire    SYNTHESIZED_WIRE_10;

wire    SYNTHESIZED_WIRE_12;

wire    SYNTHESIZED_WIRE_13;

wire    SYNTHESIZED_WIRE_16;

wire    SYNTHESIZED_WIRE_17;

wire    SYNTHESIZED_WIRE_18;

wire    SYNTHESIZED_WIRE_23;

wire    SYNTHESIZED_WIRE_24;

wire    SYNTHESIZED_WIRE_25;

wire    SYNTHESIZED_WIRE_34;

wire    SYNTHESIZED_WIRE_36;

wire    SYNTHESIZED_WIRE_38;

wire    SYNTHESIZED_WIRE_39;

wire    SYNTHESIZED_WIRE_42;

wire    SYNTHESIZED_WIRE_43;

wire    SYNTHESIZED_WIRE_44;

wire    SYNTHESIZED_WIRE_51;

wire    SYNTHESIZED_WIRE_53;

wire    SYNTHESIZED_WIRE_78;

wire    SYNTHESIZED_WIRE_84;

wire    SYNTHESIZED_WIRE_85;

wire    SYNTHESIZED_WIRE_86;

wire    SYNTHESIZED_WIRE_88;

wire    SYNTHESIZED_WIRE_90;

wire    SYNTHESIZED_WIRE_91;

wire    SYNTHESIZED_WIRE_118;

wire    SYNTHESIZED_WIRE_95;

wire    SYNTHESIZED_WIRE_96;

wire    SYNTHESIZED_WIRE_97;

wire    SYNTHESIZED_WIRE_98;

wire    SYNTHESIZED_WIRE_99;

wire    SYNTHESIZED_WIRE_100;

wire    SYNTHESIZED_WIRE_101;

wire    SYNTHESIZED_WIRE_102;

wire    SYNTHESIZED_WIRE_103;

wire    SYNTHESIZED_WIRE_104;

wire    SYNTHESIZED_WIRE_105;

wire    SYNTHESIZED_WIRE_106;

wire    SYNTHESIZED_WIRE_107;

wire    SYNTHESIZED_WIRE_108;

wire    SYNTHESIZED_WIRE_112;

wire    SYNTHESIZED_WIRE_113;

\\74163     b2v_inst(

    .ENT(input),

    .CLRN(clr),

    .CLK(clk),

    .ENP(input),

    .LDN(input),

.QA(SYNTHESIZED_WIRE_115),

.QB(SYNTHESIZED_WIRE_116),

.QC(SYNTHESIZED_WIRE_117),

.QD(SYNTHESIZED_WIRE_114)

);

assign    SYNTHESIZED_WIRE_105 = ~(SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_2 & SYNTHESIZED_WIRE_116);

assign    SYNTHESIZED_WIRE_2 =  ~SYNTHESIZED_WIRE_117;

assign    SYNTHESIZED_WIRE_113 = ~(SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6 & SYNTHESIZED_WIRE_7 & SYNTHESIZED_WIRE_8);

assign    SYNTHESIZED_WIRE_100 = ~(SYNTHESIZED_WIRE_9 & SYNTHESIZED_WIRE_10 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_12);

assign    SYNTHESIZED_WIRE_102 = ~(SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_16);

assign    SYNTHESIZED_WIRE_101 = ~(SYNTHESIZED_WIRE_17 & SYNTHESIZED_WIRE_18 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_116);

assign    SYNTHESIZED_WIRE_118 = ~(SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_23 & SYNTHESIZED_WIRE_24);

assign    SYNTHESIZED_WIRE_103 = ~(SYNTHESIZED_WIRE_25 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_116);

assign    SYNTHESIZED_WIRE_108 = ~(SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_116);

assign    SYNTHESIZED_WIRE_104 = ~(SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_34 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_36);

assign    SYNTHESIZED_WIRE_96 = ~(SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_38 & SYNTHESIZED_WIRE_39 & SYNTHESIZED_WIRE_116);

assign    SYNTHESIZED_WIRE_95 = ~(SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_43 & SYNTHESIZED_WIRE_44);

assign    SYNTHESIZED_WIRE_5 =  ~SYNTHESIZED_WIRE_114;

assign    SYNTHESIZED_WIRE_7 =  ~SYNTHESIZED_WIRE_117;

assign    SYNTHESIZED_WIRE_8 =  ~SYNTHESIZED_WIRE_116;

assign    SYNTHESIZED_WIRE_6 =  ~SYNTHESIZED_WIRE_115;

assign    SYNTHESIZED_WIRE_90 =  ~SYNTHESIZED_WIRE_117;

assign    SYNTHESIZED_WIRE_91 =  ~SYNTHESIZED_WIRE_116;

assign    SYNTHESIZED_WIRE_97 = ~(SYNTHESIZED_WIRE_51 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_116);

assign    SYNTHESIZED_WIRE_88 =  ~SYNTHESIZED_WIRE_114;

assign    SYNTHESIZED_WIRE_84 =  ~SYNTHESIZED_WIRE_114;

assign    SYNTHESIZED_WIRE_86 =  ~SYNTHESIZED_WIRE_117;

assign    SYNTHESIZED_WIRE_85 =  ~SYNTHESIZED_WIRE_115;

assign    SYNTHESIZED_WIRE_51 =  ~SYNTHESIZED_WIRE_114;

assign    SYNTHESIZED_WIRE_53 =  ~SYNTHESIZED_WIRE_117;

assign    SYNTHESIZED_WIRE_9 =  ~SYNTHESIZED_WIRE_114;

assign    SYNTHESIZED_WIRE_12 =  ~SYNTHESIZED_WIRE_116;

assign    SYNTHESIZED_WIRE_10 =  ~SYNTHESIZED_WIRE_115;

assign    SYNTHESIZED_WIRE_13 =  ~SYNTHESIZED_WIRE_114;

assign    SYNTHESIZED_WIRE_16 =  ~SYNTHESIZED_WIRE_116;

assign    SYNTHESIZED_WIRE_17 =  ~SYNTHESIZED_WIRE_114;

assign    SYNTHESIZED_WIRE_18 =  ~SYNTHESIZED_WIRE_115;

assign    SYNTHESIZED_WIRE_25 =  ~SYNTHESIZED_WIRE_114;

assign    SYNTHESIZED_WIRE_43 =  ~SYNTHESIZED_WIRE_117;

assign    SYNTHESIZED_WIRE_44 =  ~SYNTHESIZED_WIRE_116;

assign    SYNTHESIZED_WIRE_42 =  ~SYNTHESIZED_WIRE_115;

assign    SYNTHESIZED_WIRE_23 =  ~SYNTHESIZED_WIRE_117;

assign    SYNTHESIZED_WIRE_112 =  ~SYNTHESIZED_WIRE_116;

assign    SYNTHESIZED_WIRE_24 =  ~SYNTHESIZED_WIRE_116;

assign    SYNTHESIZED_WIRE_39 =  ~SYNTHESIZED_WIRE_117;

assign    SYNTHESIZED_WIRE_38 =  ~SYNTHESIZED_WIRE_115;

assign    SYNTHESIZED_WIRE_107 = ~(SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_78 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_116);

assign    SYNTHESIZED_WIRE_36 =  ~SYNTHESIZED_WIRE_116;

assign    SYNTHESIZED_WIRE_34 =  ~SYNTHESIZED_WIRE_115;

assign    SYNTHESIZED_WIRE_78 =  ~SYNTHESIZED_WIRE_115;

assign    SYNTHESIZED_WIRE_98 = ~(SYNTHESIZED_WIRE_84 & SYNTHESIZED_WIRE_85 & SYNTHESIZED_WIRE_86 & SYNTHESIZED_WIRE_116);

assign    SYNTHESIZED_WIRE_99 = ~(SYNTHESIZED_WIRE_88 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_90 & SYNTHESIZED_WIRE_91);

assign    Washing = ~(SYNTHESIZED_WIRE_118 & SYNTHESIZED_WIRE_118 & SYNTHESIZED_WIRE_118 & SYNTHESIZED_WIRE_95 & SYNTHESIZED_WIRE_96 & SYNTHESIZED_WIRE_97 & SYNTHESIZED_WIRE_98 & SYNTHESIZED_WIRE_99 & SYNTHESIZED_WIRE_100 & SYNTHESIZED_WIRE_101 & SYNTHESIZED_WIRE_102 & SYNTHESIZED_WIRE_103);

assign    Drainage = ~(SYNTHESIZED_WIRE_104 & SYNTHESIZED_WIRE_105);

assign    Dehydration = ~(SYNTHESIZED_WIRE_106 & SYNTHESIZED_WIRE_107 & SYNTHESIZED_WIRE_108);

assign    SYNTHESIZED_WIRE_106 = ~(SYNTHESIZED_WIRE_114 & SYNTHESIZED_WIRE_115 & SYNTHESIZED_WIRE_117 & SYNTHESIZED_WIRE_112);

assign    Standby =  ~SYNTHESIZED_WIRE_113;

endmodule

5、仿真结果截图

6、结果分析

当给入信号后，洗衣依次进入洗衣状态，排水状态，脱水状态，最后回到待机状态，当有复位信号 CLR=0 输入时，系统进入循环控制状态。

7、总结

    通过这次的课程设计，强化了我所学的知识，还加强了我的动手能力，在与同学讨论进行改进讨论的过程中我们的知识也不断提升。对我个人而言，我最大的收获就是学会了如何利用Quartus II进行电路仿真模拟。我明白了做实验设计应该按步骤设计：列真值表→根据真值画卡若图列出逻辑函数表达式并化简→根据化简了的逻辑表达式画出逻辑电路图→选择适当的电路芯片合理布线设计实验线路。

   做实验时需要用到很多的连接导线，在连接导线时一定要小心、耐心，根据逻辑表达式可以直接接线，但是容易接错。最快捷的接法是将芯片引脚对应逻辑电路图的输入输出端分别编号，接线时就可以直接按编号接，布局合理也非常的重要。在其中我不断地翻书，找资料。其次还学会了如何撰写设计报告，这一切都使我觉得自己受益匪浅。

8、参考文献

数字设计原理与实践（第四版）  John F. Wakerly下载本文